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determining

  • Realization of alogrithm of chaos detection by determining Lyapunov exponents.

    Realization of alogrithm of chaos detection by determining Lyapunov exponents.

    標簽: Realization determining alogrithm detection

    上傳時間: 2013-12-25

    上傳用戶:R50974

  • determining embedding dimension for phase-space reconstruction using a geometrical construction. It

    determining embedding dimension for phase-space reconstruction using a geometrical construction. It is very important reference for time forecast in chaos sequence.

    標簽: reconstruction construction determining phase-space

    上傳時間: 2013-12-23

    上傳用戶:weiwolkt

  • This chapter contains sample programs for determining capacity. The reader is advised to go through

    This chapter contains sample programs for determining capacity. The reader is advised to go through the coding. The file "capacity_water.m" is for measuring the waterfilling capacity. It should be made to work with a file similar to "capacity_plot_main.m". The latter file deals with all the other capacity plots given in the book in Chapter 2. All programs are verified with MATLAB versions 6.0 and above with signal processing and communications toolboxes.

    標簽: determining capacity contains programs

    上傳時間: 2016-08-24

    上傳用戶:yph853211

  • Useful guidelines that aid in determining when to stop testing a given software product.

    Useful guidelines that aid in determining when to stop testing a given software product.

    標簽: determining guidelines software product

    上傳時間: 2013-11-25

    上傳用戶:我干你啊

  • a file for determining a polynomial degrees

    a file for determining a polynomial degrees

    標簽: determining polynomial degrees file

    上傳時間: 2013-12-16

    上傳用戶:xuan‘nian

  • VHDL,Verilog,System verilog比較

      本文簡單討論并總結(jié)了VHDL、Verilog,System verilog 這三中語言的各自特點和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

    標簽: Verilog verilog System VHDL

    上傳時間: 2013-10-16

    上傳用戶:牛布牛

  • XAPP806 -決定DDR反饋時鐘的最佳DCM相移

    This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

    標簽: XAPP 806 DDR DCM

    上傳時間: 2013-10-15

    上傳用戶:euroford

  • XAPP806 -決定DDR反饋時鐘的最佳DCM相移

    This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

    標簽: XAPP 806 DDR DCM

    上傳時間: 2014-11-26

    上傳用戶:erkuizhang

  • VHDL,Verilog,System verilog比較

      本文簡單討論并總結(jié)了VHDL、Verilog,System verilog 這三中語言的各自特點和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

    標簽: Verilog verilog System VHDL

    上傳時間: 2014-03-03

    上傳用戶:zhtzht

  • 假近鄰法(False Nearest Neighbor, FNN)計算嵌入維的Matlab程序 文件夾說明: Main_FNN.m - 程序主函數(shù)

    假近鄰法(False Nearest Neighbor, FNN)計算嵌入維的Matlab程序 文件夾說明: Main_FNN.m - 程序主函數(shù),直接運行此文件即可 LorenzData.dll - 產(chǎn)生Lorenz時間序列 PhaSpaRecon.m - 相空間重構(gòu) fnn_luzhenbo.dll - 假近鄰計算主函數(shù) SearchNN.dll - 近鄰點搜索 buffer_SearchNN_1.dll - 近鄰點搜索緩存1 buffer_SearchNN_2.dll - 近鄰點搜索緩存2 參考文獻: M.B.Kennel, R.Brown, H.D.I.Abarbanel. determining embedding dimension for phase-space reconstruction using a geometrical construction[J]. Phys. Rev. A 1992,45:3403.

    標簽: Main_FNN Neighbor Nearest Matlab

    上傳時間: 2013-12-10

    上傳用戶:songnanhua

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