Designing a synchronous finite state machine (FSM) is a common task for a digITal
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
標簽：
synchronous
Designing
engineer
digITal
上傳時間：
2014-01-17
上傳用戶：dreamboy36
