對頁面布局的學習資料收集，有關div+css的學習，知識比較全面，僅供學習參考。
標簽： div
上傳時間： 2017-10-29
上傳用戶：就業(yè)藍啊
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上傳時間： 2014-12-23
上傳用戶：xinhaoshan2016
本文論述了狀態(tài)機的verilog編碼風格,以及不同編碼風格的優(yōu)缺點，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
標簽： Synthesis Machine Coding Styles
上傳時間： 2013-10-15
上傳用戶：dancnc
本文簡單討論并總結了VHDL、Verilog，System verilog 這三中語言的各自特點和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標簽： Verilog verilog System VHDL
上傳時間： 2013-10-16
上傳用戶：牛布牛
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上傳時間： 2013-10-17
上傳用戶：tb_6877751
Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in
標簽： Allegro-Design-Editor-Tutorial_ad e_tut
上傳時間： 2014-08-09
上傳用戶：龍飛艇
針對城市公交網絡的評價問題，在綜合考慮城市公交系統(tǒng)諸多因素的基礎上，建立了城市公交網絡系統(tǒng)的綜合評價指標體系。然后利用非負矩陣分解的知識，提取出指標體系中的主要綜合性指標。通過對銀川市現有的公交網絡進行綜合評價后發(fā)現，文中所提出的方法可以克服傳統(tǒng)的評價方法結果無明確幾何意義和主觀依賴性等缺點，從而可以更為有效的給出量化的評價結果。
上傳時間： 2013-11-13
上傳用戶：haohaoxuexi
為了實現時序電路狀態(tài)驗證和故障檢測，需要事先設計一個輸入測試序列。基于二叉樹節(jié)點和樹枝的特性，建立時序電路狀態(tài)二叉樹，按照電路二叉樹節(jié)點(狀態(tài))與樹枝(輸入)的層次邏輯關系，可以直觀和便捷地設計出時序電路測試序列。用測試序列激勵待測電路，可以驗證電路是否具有全部預定狀態(tài)，是否能夠實現預定狀態(tài)轉換。
上傳時間： 2013-10-19
上傳用戶：qitiand
波導傳輸檢波裝置用以發(fā)射機的檢波式功率監(jiān)測，是雷達導引頭發(fā)射機的一個重要組成部分。發(fā)射機產生的大功率射頻信號經過波導傳輸檢波裝置最終傳輸給天線，在大功率傳輸過程中，波導傳輸檢波裝置從大功率射頻信號中耦合出一定量進行射頻信號包絡檢波，檢波信號通過外圍電路處理可以反映發(fā)射機工作狀態(tài)，并可反饋優(yōu)化發(fā)射機工作狀態(tài)。文中介紹了波導傳輸檢波裝置的設計原理，并對設計中的一些重要環(huán)節(jié)進行了仿真，其中包括了溫度對設計的影響。
標簽： 波導傳輸檢波裝置
上傳時間： 2013-11-23
上傳用戶：哇哇哇哇哇
