The DSKs or eZdspTM LF2407 and the DMC1500 make up a table top motor
development system which allows engineers and software developers to evaluate
certain characteristics of the TMS320F240, TMS320F243, and TMS320LF2407 dsps
to determine if the processor meets the designers application requirements. Evaluators
can create software to execute onboard or expand the system in a variety of ways.
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families
(hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard
architecture that has one program memory bus and three data memory buses. These processors also provide
an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip
memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction
set, which is the basis of the operational flexibility and speed of these dsps.
The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of
digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point dsps. The
240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost,
low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital
motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While
code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing
performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary
section for device-specific features.
This paper shows the development of a 1024-point
radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available dsps and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis
applications.
Commercially available active noise control headphones rely on fixed analog controllers to drive "anti-noise" loudspeakers. Our design uses an adaptive controller to optimally cancel unwanted acoustic noise. This headphone would be particularly useful for workers who operate or work near heavy machinery and engines because the noise is selectively eliminated. Desired sounds, such as speech and warning signals, are left to be heard clearly. The adaptive control algorithm is implemented on a Texas Instruments (TI™ )
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TMS320C30GEL digital signal processor (DSP), which drives a Sony CD550 headphone/microphone system. Our experiments indicate that adaptive noise control results in a dramatic improvement in performance over fixed noise control. This improvement is due to the availability of high-performance programmable dsps and the self-optimizing and tracking
capabilities of the adaptive controller in response to the surrounding noise.
