This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting
coding, including finite field arithmetic, (Generalized) Low-Density Parity-
Check (LDPC) codes, and Reed-Solomon codes.
標(biāo)簽：
errorcorrecting
architecture
efficient
devoted
上傳時(shí)間：
2017-05-08
上傳用戶：康郎
