it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
標簽： synthesize simulator modelsim verilog
上傳時間： 2014-06-26
上傳用戶：zhuyibin
HDFDUMP and BRFDUMP are utility programs developed for use with MISR data files. HDFDUMP will extract data from a MISR file in the HDF-EOS grid format (MISR Level 1B2 and Level 2 files) and writes unformatted binary files. BRFDUMP calculates radiances and bidirectional reflectance factors (BRF) from MISR Level 1B2 files and creates unformatted binary files.
標簽： HDFDUMP developed programs BRFDUMP
上傳時間： 2017-04-02
上傳用戶：yy541071797
自己寫的是用于所有VC開發(fā)平臺和linux平臺軟件開發(fā)的trace功能函數(shù)。可自定module,evel, 系統(tǒng)時間開關(guān)，trace開關(guān)，trace level開關(guān)，輸出log 到文件，trace 存儲文件的大小。。。
上傳時間： 2017-04-05
上傳用戶：ljt101007
R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 128-byte page programming function to make their write operation faster. Note: Renesas Technology鈥檚 serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology鈥檚 sales office before using industrial applications such as automotive systems, embedded controllers, and meters
標簽： Electrically Programmable interface Erasable
上傳時間： 2014-01-07
上傳用戶：xiaohuanhuan
Abstract. The main aim of this research is to improve communication between student and teacher by using the developing mobile information technologies. Implementing such technologies in education may help to develop learning environments to share the knowledge among students and increase their motivation to possible highest level. Based on mobile equipments used in daily life an online student announcement system has been developed which aims to provide sharing of documents and communication ways between students and teachers.
標簽： communication Abstract research improve
上傳時間： 2017-04-10
上傳用戶：WMC_geophy
For a programming language, Fortran has been around a long time. It was one of the first widely used 鈥渉igh-level鈥?languages, as well as the first programming language to be standardized. It is still the premier language for scientific and engineering computing applications. The purpose of this handbook is to describe the latest version of this language, Fortran 90. This chapter gives some history of the development and standardization of Fortran and describes the notation used to specify the syntax of Fortran 90.
標簽： programming language Fortran around
上傳時間： 2014-01-04
上傳用戶：6546544
The future satellite communication systems are re- quired to support the higher transmission data rate for providing the multimedia services by employing the e鏗僣ient modulation method such as multi-level QAM.
標簽： communication transmission satellite systems
上傳時間： 2017-04-18
上傳用戶：busterman
The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
標簽： implementation instruction multiple purpose
上傳時間： 2017-04-18
上傳用戶：731140412
ecos RTOS 原理介紹和應用開發(fā)The design philosophy of eCos was to augment an open-source RTOS (which meant no per-unit royalties) with source-level con?guration tools that would enable embedded developers to scale their RTOS from hundreds of bytes to hundreds of kilobytes without needing to manu- ally change a line of source code.
標簽： RTOS open-source philosophy augment
上傳時間： 2013-12-16
上傳用戶：天涯
The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
標簽： increasingly description designing languages
上傳時間： 2014-01-08
上傳用戶：小草123
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