This examPLe sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The
clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA is setup to generate a periodic ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
標(biāo)簽：
SYSCLKOUT
examPLe
divides
HSPCLK
上傳時(shí)間：
2014-01-25
上傳用戶：ljt101007
