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基于Virtex5的PCI接口電路

PCI express是由Intel，Dell，Compaq，IBM，Microsoft等PCI SIG聯(lián)合成立的Arapahoe Work Group共同草擬并推舉成取代PCI總線標(biāo)準(zhǔn)的下一代標(biāo)準(zhǔn)。PCI express利用串行的連接特點(diǎn)能輕松將數(shù)據(jù)傳輸速度提到一個(gè)很高的頻率，達(dá)到遠(yuǎn)遠(yuǎn)超出PCI總線的傳輸速率。一個(gè)PCI express連接可以被配置成x1，x2，x4，x8，x12，x16和x32的數(shù)據(jù)帶寬。x1的通道能實(shí)現(xiàn)單向312.5 MB／s（2.5 Gb／s）的傳輸速率。Xilinx公司的Virtex5系列FPGA芯片內(nèi)嵌PCI-expressEndpoint Block硬核，為實(shí)現(xiàn)單片可配置PCI-express總線解決方案提供了可能。　　本文在研究PCI-express接口協(xié)議和PCI-express Endpoint Block硬核的基礎(chǔ)上，使用Virtex5LXT50 FPGA芯片設(shè)計(jì)PCI express接口硬件電路，實(shí)現(xiàn)PCI-express數(shù)據(jù)傳輸

標(biāo)簽： Virtex5 PCI 接口電路

上傳時(shí)間： 2013-12-27

上傳用戶：wtrl

利用WinDriver實(shí)現(xiàn)鏈?zhǔn)紻MA

PCI express 協(xié)議由于其高速串行、系統(tǒng)拓?fù)浜唵蔚忍攸c(diǎn)被廣泛用于各種領(lǐng)域。Altera公司的Arria II GX FPGA內(nèi)集成了支持鏈?zhǔn)紻MA傳輸功能的PCI express硬核，適應(yīng)了PCI express總線高速度的要求。文中利用Jungo公司的WinDriver軟件實(shí)現(xiàn)了鏈?zhǔn)紻MA的上層應(yīng)用設(shè)計(jì)。首先給出了鏈?zhǔn)紻MA實(shí)現(xiàn)的基本過程，接著分析了鏈?zhǔn)紻MA數(shù)據(jù)傳輸需要處理的幾個(gè)問題，給出了相應(yīng)的解決辦法和策略。采用這些方法，保證了DAM數(shù)據(jù)傳輸?shù)恼_性，簡化了底層FPGA應(yīng)用邏輯的設(shè)計(jì)。

標(biāo)簽： WinDriver DMA 上傳時(shí)間： 2014-12-22

采用低成本FPGA實(shí)現(xiàn)高效的低功耗PCIe接口

　　白皮書：采用低成本FPGA實(shí)現(xiàn)高效的低功耗PCIe接口 　　了解一個(gè)基于DDR3存儲(chǔ)器控制器的真實(shí)PCI express® （PCIe®） Gen1x4參考設(shè)計(jì)演示高效的Cyclone V FPGA怎樣降低系統(tǒng)總成本，同時(shí)實(shí)現(xiàn)性能和功耗目標(biāo)。點(diǎn)擊馬上下載！

標(biāo)簽： FPGA PCIe 低功耗 接口

上傳時(shí)間： 2013-10-18

上傳用戶：康郎

支持PCI express的4Gbps光纖通道控制器

PCIe規(guī)范，光纖通道控制器

標(biāo)簽： express 4Gbps PCI 光纖通道

上傳時(shí)間： 2013-10-21

上傳用戶：ppeyou

WP362-利用設(shè)計(jì)保存功能實(shí)現(xiàn)可重復(fù)的結(jié)果

  　　FPGA 設(shè)計(jì)不再像過去一樣只是作為“膠連邏輯 (Gluelogic)”了，由于其復(fù)雜度逐年增加，通常還會(huì)集成極富挑戰(zhàn)性的 IP 核，如 PCI express® 核等。新型設(shè)計(jì)中的復(fù)雜模塊即便不作任何改變也會(huì)在滿足 QoR(qualityof-result) 要求方面遇到一些困難。保留這些模塊的時(shí)序非常耗時(shí)，既讓人感到頭疼，往往還徒勞無功。設(shè)計(jì)保存流程可以幫助客戶解決這一難題，既可以讓他們滿足設(shè)計(jì)中關(guān)鍵模塊的時(shí)序要求，又能在今后重用實(shí)現(xiàn)的結(jié)果，從而顯著減少時(shí)序收斂過程中的運(yùn)行次數(shù)。

標(biāo)簽： 362 WP 重復(fù)

上傳時(shí)間： 2013-11-20

上傳用戶：invtnewer

基于FPGA實(shí)現(xiàn)的高速串行交換模塊實(shí)現(xiàn)方法研究

采用Xlinx公司的Virtex5系列FPGA設(shè)計(jì)了一個(gè)用于多種高速串行協(xié)議的數(shù)據(jù)交換模塊,并解決了該模塊實(shí)現(xiàn)中的關(guān)鍵問題.該交換模塊實(shí)現(xiàn)4X模式RapidIO協(xié)議與4X模式PCI express協(xié)議之間的數(shù)據(jù)交換,以及自定義光纖協(xié)議與4X模式PCI express協(xié)議之間的數(shù)據(jù)交換,實(shí)現(xiàn)了單字讀寫以及DMA操作,并提供高速穩(wěn)定的傳輸帶寬.

標(biāo)簽： FPGA 高速串行 模塊 實(shí)現(xiàn)方法

上傳時(shí)間： 2013-10-19

上傳用戶：angle

Virtex-5 GTP Transceiver Wizar

The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

標(biāo)簽： Transceiver Virtex Wizar GTP

上傳時(shí)間： 2013-10-20

上傳用戶：dave520l

UG341-LogiCORE Endpoint Block

UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI express® 用戶指南

標(biāo)簽： LogiCORE Endpoint Block 341

上傳時(shí)間： 2013-10-17

上傳用戶：jeffery

pci e PCB設(shè)計(jì)規(guī)范

This document provides practical, common guidelines for incorporating PCI express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范

上傳時(shí)間： 2014-01-24

上傳用戶：s363994250

賽靈思電機(jī)控制開發(fā)套件簡介（英文版）

　　The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 　　Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. 　　The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.

標(biāo)簽： 賽靈思 電機(jī)控制 開發(fā)套件 英文

上傳時(shí)間： 2013-10-28

上傳用戶：wujijunshi