首先研究CAN總線和SAE J1939協(xié)議，提出一種基于MC9S12HZ256微控制器的總線式汽車數(shù)字儀表解決方案。詳細(xì)介紹SAE J1939協(xié)議的報(bào)文幀格式及應(yīng)用層協(xié)議中發(fā)動(dòng)機(jī)相關(guān)參數(shù)的定義，以及步進(jìn)電機(jī)及其驅(qū)動(dòng)和車速信號(hào)的處理方法。該數(shù)字儀表系統(tǒng)硬件平臺(tái)由微處理器和信號(hào)采集和信息處理及顯示等模塊組成。軟件設(shè)計(jì)部分編程實(shí)現(xiàn)了對(duì)CAN總線和各傳感器數(shù)據(jù)的讀取、處理。該系統(tǒng)能夠?qū)崟r(shí)反映車輛工況。 Abstract: In this paper，CAN bus and SAE J1939protocol are researched，and a vehicle digital instrument solution based on MC9S12HZ256MCU is proposed.The message frame forMAT and some engine-related parameters’definition in SAE J1939application layer protocol are introduced in detail.Stepper motor and its driver，the methods of speed signal process-ing are also introduced.The hardware platform of vehicle digital instrument is composed by MCU，signal acquisition mod-ule，and signal processing and displaying module.Data receiving and processing from CAN bus and sensors are accom-plished by programming，and vehicle condition can be reflected in real-time.
上傳時(shí)間： 2013-10-20
上傳用戶：huannan88
1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 lines of up to 12 characters per line· 5 ′ 7 character forMAT plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
標(biāo)簽： 2116 PCF LCD 驅(qū)動(dòng)器芯片
上傳時(shí)間： 2013-11-08
上傳用戶：laozhanshi111
This overview guide describes all the peripherals available for TMS320x28xx and TMS320x28xxx devices.Section 2 shows the peripherals used by each device. Section 3 provides descriptions of the peripherals.You can download the peripheral guide by clicking on the literature number, which is linked to the portable document forMAT (pdf) file.
標(biāo)簽： 281x Dsp 281 外設(shè)
上傳時(shí)間： 2013-11-21
上傳用戶：HGH77P99
This application note provides users with a general understanding of the SVF and XSVF fileforMATs as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For inforMATion on using Serial Vector forMAT (SVF) and Xilinx Serial Vector forMAT(XSVF) files in embedded programming applications
標(biāo)簽： Xilinx XAPP XSVF 503
上傳時(shí)間： 2013-10-21
上傳用戶：tiantwo
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p forMAT, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
1 Communication Protocol (Computer as master) The communication protocol describes here allows your computer to access 4096 internal registers (W0000-W4095) and 1024 internal relays (B0000-B1023) in the Workstation.. 1.1 Request Message forMAT Request message is a command message to be sent from the computer to the Workstation. The data structure of request message is shown below. Note that numbers are always in hexadecimal form and converted into ASCII characters. For example, Workstation unit number 14 will appear in the message as character 0(30h) followed by character E(45h); a BCC of 5Ah will appear in the message as character 5(35h) followed by character A(41h).
上傳時(shí)間： 2013-10-28
上傳用戶：cxl274287265
ORCAD在使用的時(shí)候總會(huì)出現(xiàn)這樣或那樣的問題…但下這個(gè)問題比較奇怪…在ORCAD中無法輸出網(wǎng)表…彈出下面的錯(cuò)誤….這種問題很是奇怪…Netlist forMAT: tango.dllDesign Name: D:\EDA_PROJECT\PROTEL99SE\YK\SV3200\MAIN.DSNERROR [NET0021] Cannot get part.[FMT0024] Ref-des not found. Possible Logical/Physical annotation conflict.[FMT0018] Errors processing intermediate file找了一天沒找到問題…終于在花了N多時(shí)間后發(fā)現(xiàn)問題所在…其實(shí)這個(gè)問題就是不要使用ORCAD PSPICE 庫里面的元件來畫電路圖…實(shí)際中我是用了PSPICE里面和自己制作的二種電阻和電容混合在一起…就會(huì)出現(xiàn)這種問題…
上傳時(shí)間： 2013-11-21
上傳用戶：zaocan888
This application note provides users with a general understanding of the SVF and XSVF fileforMATs as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For inforMATion on using Serial Vector forMAT (SVF) and Xilinx Serial Vector forMAT(XSVF) files in embedded programming applications
標(biāo)簽： Xilinx XAPP XSVF 503
上傳時(shí)間： 2015-01-02
上傳用戶：時(shí)代將軍
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p forMAT, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the forMAT A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2013-11-20
上傳用戶：pzw421125
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