Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gateS cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
標簽： Solutions Analog Altera FPGAs
上傳時間： 2013-11-08
上傳用戶：蟲蟲蟲蟲蟲蟲
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gateS, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時間： 2013-12-10
上傳用戶：zgu489
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gateS cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
標簽： Solutions Analog Altera FPGAs
上傳時間： 2013-10-27
上傳用戶：fredguo
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gateS cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標簽： Solutions Analog Xilinx FPGAs
上傳時間： 2013-11-07
上傳用戶：suicone
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gateS, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時間： 2013-10-21
上傳用戶：ligi201200
WHAT MIME64 IS: MIME64 is an encoding described in RFC1341 as MIME base64.Its purpose is to encode binary files into ASCII so that they may be passedthrough e-mail gateS. In this regard, MIME64 is similar to UUENCODE.Although most binaries these days are transmitted using UUENCODE, Ihave seen a few using MIME64, and I have had requests from friends thatI decode MIME64 files that have fallen into their hands. As long assome MIME64 continues to exist, a package such as this one is usefulto have.
標簽： MIME described 64 encoding
上傳時間： 2013-12-17
上傳用戶：maizezhen
十年前，微軟帝國的締造者比爾-蓋茨(Bill gateS)曾撰寫過一本在當時轟動一時的書——《未來之路》，他在這本276頁的書中預測了微軟乃至整個科技產業未來的走勢。蓋茨在書中寫道：“雖然現在看來這些預測不太可能實現，甚至有些荒謬，但是我保證這是本嚴肅的書，而決不是戲言。十年后我的觀點將會得到證實?！币晦D眼十年過去了，現在讓我們回顧一下蓋茨的書中到底預測了些什么，又有哪些已經成為了現實。
標簽：
上傳時間： 2013-12-23
上傳用戶：541657925
The objective of this projectis to design, model and simulate an autocorrelation generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some gateS. By the autocorrelation concept, there should be 2 same length vectors, for calculating the autocorrelation , we have to design the register for storing the original vector and the shifter for make time delay.
標簽： autocorrelation objective generator projectis
上傳時間： 2015-08-17
上傳用戶：ikemada
this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & gateS to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
標簽： implementation include quartus source
上傳時間： 2013-12-25
上傳用戶：壞壞的華仔
This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gateS, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools.
標簽： illustrate diversity selection contains
上傳時間： 2016-06-06
上傳用戶：yimoney
