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general-purpose

  • 紅外動(dòng)目標(biāo)識(shí)別跟蹤系統(tǒng)DSPFPGA硬件設(shè)計(jì)與實(shí)現(xiàn)

    視頻目標(biāo)識(shí)別與跟蹤技術(shù)是當(dāng)今世界重要的研究課題,它涉及圖像處理、自動(dòng)控制、計(jì)算機(jī)應(yīng)用等學(xué)科,該文主要論述該項(xiàng)目的具體實(shí)現(xiàn)及相關(guān)理論分析,重點(diǎn)在于該系統(tǒng)的硬件模塊實(shí)現(xiàn)及分析.該系統(tǒng)的硬件模塊是典型的高速數(shù)字電路,這也是當(dāng)今世界電路設(shè)計(jì)的一大熱點(diǎn).同時(shí),該系統(tǒng)的硬件模塊不同于傳統(tǒng)的模擬、數(shù)字電路.嚴(yán)格的說它是基于可編程芯片的系統(tǒng)(System On Programmable Chip).它與傳統(tǒng)電路的最大不同在于,硬件模塊本身不具備任何功能,但該硬件模塊可以與相應(yīng)的軟件結(jié)合(此處,我們將FPGA中的可編程指令也廣義的歸入軟件范疇),實(shí)現(xiàn)相應(yīng)的功能.換言之,該硬件模塊通過換用其他軟件,可以實(shí)現(xiàn)其他功能.所以從這個(gè)意義上講,我們也可以將其稱為基于可編程芯片的通用平臺(tái)系統(tǒng)(General System On Programmable Chip).此外,該文還對該系統(tǒng)進(jìn)行了嘗試性的層狀結(jié)構(gòu)描述,這種描述同樣適用于其它IT目的或電子系統(tǒng).

    標(biāo)簽: DSPFPGA 紅外 目標(biāo)識(shí)別 硬件設(shè)計(jì)

    上傳時(shí)間: 2013-04-24

    上傳用戶:yumiaoxia

  • 如何用ST7 PWM ST7 BRM產(chǎn)生模擬信號(hào)輸出(50Hz正弦波)

    The purpose of this note is to present how to use the ST7 PWM/BRM for the generation of a50Hz si

    標(biāo)簽: ST7 PWM BRM 50

    上傳時(shí)間: 2013-06-01

    上傳用戶:huyanju

  • LM621無刷電機(jī)換向器

    General Description The LM621 is a bipolar IC designed for commutation of brushless DC motors. The part is compatible with both three- and four-phase motors. It can directly drive the power switching devices used to drive the motor. The LM621 provides an adjustable dead-time circuit to eliminate ``shootthrough'' current spiking in the power switching circuitry. Operation is from a 5V supply, but output swings of up to 40V are accommodated. The part is packaged in an 18-pin, dual-in-line package.

    標(biāo)簽: 621 LM 無刷電機(jī)

    上傳時(shí)間: 2013-07-24

    上傳用戶:sdq_123

  • 高精度I2C實(shí)時(shí)時(shí)鐘的設(shè)計(jì)

    Abstract: This application note presents an overview of the operational characteristics of accurate I²C real-time clocks (RTCs),including the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of device resources forpower management, I²C communication circuit configurations, and I²C characteristics relative to device power-up sequences andinitializations. Additional discussions on decoupling are provided to support developing strategies for mitigating power-supply pushingof device frequency.

    標(biāo)簽: I2C 高精度 實(shí)時(shí)時(shí)鐘

    上傳時(shí)間: 2013-11-23

    上傳用戶:WMC_geophy

  • 利用數(shù)字電位器調(diào)整并校準(zhǔn)升壓型DC-DC轉(zhuǎn)換器

    The purpose of this application note is to show an example of how a digital potentiometer can be used in thefeedback loop of a step-up DC-DC converter to provide calibration and/or adjustment of the output voltage.The example circuit uses a MAX5025 step-up DC-DC converter (capable of generating up to 36V,120mWmax) in conjunction with a DS1845, 256 position, NV digital potentiometer. For this example, the desiredoutput voltage is 32V, which is generated from an input supply of 5V. The output voltage can be adjusted in35mV increments (near 32V) and span a range wide enough to account for resistance, potentiometer and DCDCconverter tolerances (27.6V to 36.7V).

    標(biāo)簽: DC-DC 數(shù)字電位器 升壓型 校準(zhǔn)

    上傳時(shí)間: 2014-12-23

    上傳用戶:781354052

  • 意法半導(dǎo)體運(yùn)放穩(wěn)定性

      Who has never experienced oscillations issues when using an operational amplifier? Opampsare often used in a simple voltage follower configuration. However, this is not the bestconfiguration in terms of capacitive loading and potential risk of oscillations.Capacitive loads have a big impact on the stability of operational amplifier-basedapplications. Several compensation methods exist to stabilize a standard op-amp. Thisapplication note describes the most common ones, which can be used in most cases.The general theory of each compensation method is explained, and based on this, specific

    標(biāo)簽: 半導(dǎo)體 運(yùn)放 穩(wěn)定性

    上傳時(shí)間: 2013-10-28

    上傳用戶:chenbhdt

  • DA轉(zhuǎn)換接口的射頻IQ調(diào)制

      Linear Technology’s High Frequency Product lineupincludes a variety of RF I/Q modulators. The purpose ofthis application note is to illustrate the circuits requiredto interface these modulators with several popular D/Aconverters. Such circuits typically are required to maximizethe voltage transfer from the DAC to the baseband inputsof the modulator, as well as provide some reconstructionfi ltering.

    標(biāo)簽: DA轉(zhuǎn)換 接口 射頻 調(diào)制

    上傳時(shí)間: 2013-10-19

    上傳用戶:FreeSky

  • PCI ExpressTM Architecture

    PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.  The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification.  No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.

    標(biāo)簽: Architecture ExpressTM PCI

    上傳時(shí)間: 2013-11-03

    上傳用戶:gy592333

  • PCB Design Considerations and Guidelines for 0.4mm and 0.5mm WLPs

    Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.

    標(biāo)簽: Considerations Guidelines and Design

    上傳時(shí)間: 2013-10-14

    上傳用戶:ysystc699

  • pcb layout規(guī)則

    LAYOUT REPORT .............. 1   目錄.................. 1     1. PCB LAYOUT 術(shù)語解釋(TERMS)......... 2     2. Test Point : ATE 測試點(diǎn)供工廠ICT 測試治具使用............ 2     3. 基準(zhǔn)點(diǎn) (光學(xué)點(diǎn)) -for SMD:........... 4     4. 標(biāo)記 (LABEL ING)......... 5     5. VIA HOLE PAD................. 5     6. PCB Layer 排列方式...... 5     7.零件佈置注意事項(xiàng) (PLACEMENT NOTES)............... 5     8. PCB LAYOUT 設(shè)計(jì)............ 6     9. Transmission Line ( 傳輸線 )..... 8     10.General Guidelines – 跨Plane.. 8     11. General Guidelines – 繞線....... 9     12. General Guidelines – Damping Resistor. 10     13. General Guidelines - RJ45 to Transformer................. 10     14. Clock Routing Guideline........... 12     15. OSC & CRYSTAL Guideline........... 12     16. CPU

    標(biāo)簽: layout pcb

    上傳時(shí)間: 2013-12-20

    上傳用戶:康郎

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