This simulation script set allows for an OFDM transmission to be
simulated. Imagetx.m generates the OFDM signal, saving it as a
windows WAV file. This allows the OFDM signal to be played out a sound
card and recorded back. Imagerx.m decodes the WAV to extract the
data.
This sample program generates two sine waves called X and Y.
It will then calculate the normalized magnitude and phase of
the two waveforms using the following formulas:
Mag = sqrt(X^2 + Y^2)/sqrt(GainX^2 + GainY^2)
Phase = (long) (atan2PU(X,Y) * 360)
The program will prompt the user to change the gain and
frequency of the X and Y waveforms.
高的工作電壓高達(dá)100V N雙N溝道MOSFET同步驅(qū)動(dòng) The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.
用戶(hù)程序示例教程
The Blinky project is a simple program for the LPC2138using Keil MCB2130 Microcontroller Board.
It blinks the LEDs at speed according to the Potentiometer setting and prints the current seting to the Serial Port 1.In addition it generates a sine wave with an adjustable frequency on the speaker of the board.
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
