Introduction jSMPP is a java implementation (SMPP API) of the SMPP protocol (currently supports SMPP v3.4). It provides interfaces to communicate with a Message Center or an ESME (External Short Message Entity) and is able to handle traffic of 3000-5000 messages per second. jSMPP is not a high-level library. People looking for a quick way to get started with SMPP may be better of using an abstraction layer such as the Apache Camel SMPP component: http://camel.apache.org/smpp.html Travis-CI status: History The project started on Google Code: http://code.google.com/p/jsmpp/ It was maintained by uudashr on Github until 2013. It is now a community project maintained at http://jsmpp.org Release procedure mvn deploy -DperformRelease=true -Durl=https://oss.sonatype.org/service/local/staging/deploy/maven2/ -DrepositoryId=sonatype-nexus-staging -Dgpg.passphrase=<yourpassphrase> log in here: https://oss.sonatype.org click the 'Staging Repositories' link select the repository and click close select the repository and click release License Copyright (C) 2007-2013, Nuruddin Ashr uudashr@gmail.com Copyright (C) 2012-2013, Denis Kostousov denis.kostousov@gmail.com Copyright (C) 2014, Daniel Pocock http://danielpocock.com Copyright (C) 2016, Pim Moerenhout pim.moerenhout@gmail.com This project is licensed under the Apache Software License 2.0.
上傳時間： 2019-01-25
上傳用戶：dragon_longer
Fundamentals of WiMAX was consciously written to appeal to a broad audience, and to be of value to anyone who is interested in the IEEE 802.16e standards or wireless broadband networks more generally. The book contains cutting-edge tutorials on the technical and theoretical under- pinnings to WiMAX that are not available anywhere else, while also providing high-level over- views that will be informative to the casual reader.
標簽： Understanding Fundamentals WiMAX of
上傳時間： 2020-05-27
上傳用戶：shancjb
Our original effort in writing this book was to create a starting point for those in the business community who did not have a high level of technical expertise but needed to have some understanding of the technical functions of their information and communication technologies (ICT) in a corporate environment. As was true with the first edition of this book, if you are already an engineer, find some other form of pleasure reading—this text is not designed for you!
標簽： Communications Introduction Technologies to
上傳時間： 2020-05-27
上傳用戶：shancjb
Before delving into the details of orthogonal frequency division multiplexing (OFDM), relevant background material must be presented first. The purpose of this chapter is to provide the necessary building blocks for the development of OFDM principles. Included in this chapter are reviews of stochastic and random process, discrete-time signals and systems, and the Discrete Fourier Transform (DFT). Tooled with the necessary mathematical foundation, we proceed with an overview of digital communication systems and OFDM communication systems. We conclude the chapter with summaries of the OFDM wireless LAN standards currently in existence and a high-level comparison of single carrier systems versus OFDM.
上傳時間： 2020-05-31
上傳用戶：shancjb
If one examines the current literature on GPS receiver design, most of it is quite a bit above the level of the novice. It is taken for granted that the reader is already at a fairly high level of understanding and proceeds from there. This text will be an attempt to take the reader through the concepts and circuits needed to be able to understand how a GPS receiver works from the antenna to the solution of user position.
標簽： Fundamentals_of_Global_Positionin g_System
上傳時間： 2020-06-09
上傳用戶：shancjb
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標簽： 4channel transla level 9519
上傳時間： 2013-11-19
上傳用戶：jisiwole
The P89LPC938 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC938 in order to reduce component count, board space, and system cost.
標簽： microcontroller single-chip available packages
上傳時間： 2013-12-04
上傳用戶：遠遠ssad
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2014-01-02
上傳用戶：二驅蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2017-07-05
上傳用戶：zhoujunzhen
