-
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel inTERFACES in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
標(biāo)簽：
314x
LPC
314
ARM
上傳時(shí)間：
2013-10-11
上傳用戶：yuchunhai1990
-
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinTERFACES in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
標(biāo)簽：
315x
LPC
315
ARM
上傳時(shí)間：
2014-01-17
上傳用戶：Altman
-
解壓密碼：www.elecfans.com 隨著微電子技術(shù)的迅速發(fā)展以及集成電路規(guī)模不斷提高，對(duì)電路性能的設(shè)計(jì)
要求越來(lái)越嚴(yán)格，這勢(shì)必對(duì)用于大規(guī)模集成電路設(shè)計(jì)的EDA 工具提出越來(lái)越高的
要求。自1972 年美國(guó)加利福尼亞大學(xué)柏克萊分校電機(jī)工程和計(jì)算機(jī)科學(xué)系開(kāi)發(fā)
的用于集成電路性能分析的電路模擬程序SPICE（Simulation Program with IC
Emphasis）誕生以來(lái)，為適應(yīng)現(xiàn)代微電子工業(yè)的發(fā)展，各種用于集成電路設(shè)計(jì)的
電路模擬分析工具不斷涌現(xiàn)。HSPICE 是Meta-Software 公司為集成電路設(shè)計(jì)中
的穩(wěn)態(tài)分析，瞬態(tài)分析和頻域分析等電路性能的模擬分析而開(kāi)發(fā)的一個(gè)商業(yè)化通
用電路模擬程序，它在柏克萊的SPICE（1972 年推出），MicroSim公司的PSPICE
（1984 年推出）以及其它電路分析軟件的基礎(chǔ)上，又加入了一些新的功能，經(jīng)
過(guò)不斷的改進(jìn)，目前已被許多公司、大學(xué)和研究開(kāi)發(fā)機(jī)構(gòu)廣泛應(yīng)用。HSPICE 可
與許多主要的EDA 設(shè)計(jì)工具，諸如Candence,Workview 等兼容，能提供許多重要
的針對(duì)集成電路性能的電路仿真和設(shè)計(jì)結(jié)果。采用HSPICE 軟件可以在直流到高
于100MHz 的微波頻率范圍內(nèi)對(duì)電路作精確的仿真、分析和優(yōu)化。在實(shí)際應(yīng)用中，
HSPICE能提供關(guān)鍵性的電路模擬和設(shè)計(jì)方案，并且應(yīng)用HSPICE進(jìn)行電路模擬時(shí)，
其電路規(guī)模僅取決于用戶計(jì)算機(jī)的實(shí)際存儲(chǔ)器容量。
The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming inTERFACES (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
標(biāo)簽：
download
hspice
2007
上傳時(shí)間：
2013-11-10
上傳用戶：123312
-
Today in many applications such as network switches, routers, multi-computers,and processor-memory inTERFACES, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽：
時(shí)鐘恢復(fù)
英文
上傳時(shí)間：
2013-10-30
上傳用戶：ysjing
-
使用Nios II軟件構(gòu)建工具
This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and
scripts that creates and builds embedded C/C++ application projects, user library
projects, and board support packages (BSPs). The Nios II SBT supports a repeatable,
scriptable, and archivable process for creating your software product.
You can invoke the Nios II SBT through either of the following user inTERFACES:
■ The Eclipse™ GUI
■ The Nios II Command Shell
The purpose of this chapter is to make you familiar with the internal functionality of
the Nios II SBT, independent of the user interface employed.
標(biāo)簽：
Nios
軟件
上傳時(shí)間：
2013-10-12
上傳用戶：china97wan
-
The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O inTERFACES in their designs. One aspect ofdesign that plays an increasingly important role isthat of the FPGA package. As the inTERFACES get fasterand wider, choosing the right package has becomeone of the key considerations for the systemdesigner.
標(biāo)簽：
Virtex
247
WP
高級(jí)封裝
上傳時(shí)間：
2013-11-07
上傳用戶：wanghui2438
-
Consumer display applications commonly use high-speed LVDS inTERFACES to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽：
Spartan
XAPP
1065
FPGA
上傳時(shí)間：
2013-11-01
上傳用戶：hjkhjk
-
解壓密碼：www.elecfans.com 隨著微電子技術(shù)的迅速發(fā)展以及集成電路規(guī)模不斷提高，對(duì)電路性能的設(shè)計(jì)
要求越來(lái)越嚴(yán)格，這勢(shì)必對(duì)用于大規(guī)模集成電路設(shè)計(jì)的EDA 工具提出越來(lái)越高的
要求。自1972 年美國(guó)加利福尼亞大學(xué)柏克萊分校電機(jī)工程和計(jì)算機(jī)科學(xué)系開(kāi)發(fā)
的用于集成電路性能分析的電路模擬程序SPICE（Simulation Program with IC
Emphasis）誕生以來(lái)，為適應(yīng)現(xiàn)代微電子工業(yè)的發(fā)展，各種用于集成電路設(shè)計(jì)的
電路模擬分析工具不斷涌現(xiàn)。HSPICE 是Meta-Software 公司為集成電路設(shè)計(jì)中
的穩(wěn)態(tài)分析，瞬態(tài)分析和頻域分析等電路性能的模擬分析而開(kāi)發(fā)的一個(gè)商業(yè)化通
用電路模擬程序，它在柏克萊的SPICE（1972 年推出），MicroSim公司的PSPICE
（1984 年推出）以及其它電路分析軟件的基礎(chǔ)上，又加入了一些新的功能，經(jīng)
過(guò)不斷的改進(jìn)，目前已被許多公司、大學(xué)和研究開(kāi)發(fā)機(jī)構(gòu)廣泛應(yīng)用。HSPICE 可
與許多主要的EDA 設(shè)計(jì)工具，諸如Candence,Workview 等兼容，能提供許多重要
的針對(duì)集成電路性能的電路仿真和設(shè)計(jì)結(jié)果。采用HSPICE 軟件可以在直流到高
于100MHz 的微波頻率范圍內(nèi)對(duì)電路作精確的仿真、分析和優(yōu)化。在實(shí)際應(yīng)用中，
HSPICE能提供關(guān)鍵性的電路模擬和設(shè)計(jì)方案，并且應(yīng)用HSPICE進(jìn)行電路模擬時(shí)，
其電路規(guī)模僅取決于用戶計(jì)算機(jī)的實(shí)際存儲(chǔ)器容量。
The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming inTERFACES (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
標(biāo)簽：
download
hspice
2007
上傳時(shí)間：
2013-10-18
上傳用戶：s363994250
-
Abstract: How can an interface change a happy face to a sad face? Engineers have happy faces when an interface works properly.Sad faces indicate failure somewhere. Because inTERFACES between microprocessors and ICs are simple—even easy—they are oftenignored until interface failure causes sad faces all around. In this article, we discuss a common SPI error that can be almostimpossible to find in a large system. Links to interface tutorial information are provided for complete information. Noise as a systemissue and ICs to minimize its effects are also described.
標(biāo)簽：
集成電路
通用接口
上傳時(shí)間：
2013-11-18
上傳用戶：zgz317
-
ngrep strives to provide most of GNU grep s common features, applying them to the network layer. ngrep is a pcap-aware tool that will allow you to specify extended regular or hexadecimal expressions to match against data payloads of packets. It currently recognizes TCP, UDP and ICMP across Ethernet, PPP, SLIP, FDDI, Token Ring and null inTERFACES, and understands bpf filter logic in the same fashion as more common packet sniffing tools, such as tcpdump and snoop.
標(biāo)簽：
applying
features
network
strives
上傳時(shí)間：
2014-01-15
上傳用戶：bcjtao
