<table id="0c80g"></table> hide markov model(HMM) for matlab including initiate,train,and test three parts
標(biāo)簽： including initiate markov matlab
上傳時(shí)間： 2015-11-10
上傳用戶：bruce
JRemoteControl is a simple Java™ driven bluetooth remote control.It allows you to initiate virtually any task on your PC from a J2ME enabled device.
標(biāo)簽： JRemoteControl bluetooth initiate control
上傳時(shí)間： 2016-04-22
上傳用戶：1583060504
The Infineon TriCore provides an Interrupt System with a high safety standard. Thisdocument contains some instructions on how to initiate an Interrupt from an externaldevice. First it will show you how to trigger an Interrupt Service Request by an impulseon Port 0 or Port 1. Then in the second part of the document you can find hints how todebounce impulses to enable the use of a simple switch as input device.Authors: Thomas Bliem, CQ Nguyen / Infineon SMI MD Apps
標(biāo)簽： TriCore 外部設(shè)備 中斷 微控制器
上傳時(shí)間： 2013-11-05
上傳用戶：uuuuuuu
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
標(biāo)簽： routines slave I2C 87L
上傳時(shí)間： 2013-11-19
上傳用戶：shirleyYim
KphoneSI (kpsi) is a SIP (Session Initiation Protocol) user agent for Linux, with which you can initiate VoIP (Voice over IP) connections over the Internet, send Instant Messages, subscribe your friends presence information and start other applications of your choice
標(biāo)簽： Initiation KphoneSI Protocol Session
上傳時(shí)間： 2015-09-13
上傳用戶：sy_jiadeyi
Hammerhead2 is a stress testing tool designed to test out your web server and web site. It can initiate multiple connections from IP aliases and simulated numerous (256+) users at any given time
標(biāo)簽： Hammerhead2 web designed testing
上傳時(shí)間： 2016-01-04
上傳用戶：youlongjian0
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標(biāo)簽： bus bidirectional primarily designed
上傳時(shí)間： 2013-12-11
上傳用戶：jeffery
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
標(biāo)簽： configures the selects channel
上傳時(shí)間： 2013-12-09
上傳用戶：
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
標(biāo)簽： configures the selects channel
上傳時(shí)間： 2016-12-24
上傳用戶：朗朗乾坤
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin is restarted. The ACQMOD bit in the input control byte offer+ CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval.
標(biāo)簽： configures the selects channel
上傳時(shí)間： 2016-12-24
上傳用戶：yzhl1988
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