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keil c51 v9.01此版不是漢化中文版，是英文版來的。ARM發布Keil μVision4集成開發環境(IDE)，用來在微控制器和智能卡設備上創建、仿真和調試嵌入式應用。
μVision4 IDE是為增強開發人員的工作效率設計的，有了它可以更快速、更高效地開發和檢驗程序。通過μVision4 IDE中引入的靈活的窗口管理系統，開發人員可以使用多臺監視器，在可視界面任何地方全面控制窗口放置。
新用戶界面可以更好地利用屏幕空間，更有效地組織多個窗口，為開發應用提供整齊高效的環境。
μVision4在μVision3的成功經驗的基礎上增加了：* System Viewer (系統查看程序)窗口，提供了設備外圍寄存器信息，這些信息可以在System Viewer窗口內部直接更改。* Debug Restore Views (調試恢復視圖)允許保存多個窗口布局，為程序分析迅速選擇最適合的調試視圖。* Multi-Project Workspace(多項目工作空間)為處理多個并存的項目提供了簡化的方法，如引導加載程序和應用程序。* 為基于ARM Cortex 處理器的MCU提供了Data and instruction trace(數據和指令追蹤)功能。* 擴展了Device Simulation(設備仿真)功能以支持許多新設備，如Luminary、NXP和東芝生產的基于ARM Cortex-M3處理器的MCU；Atmel SAM7/9；及新的8051衍生品，如Infineon XC88x和SiLABS 8051Fxx。* 支持許多debug adapter interfaces(調試適配器接口)，包括ADI miDAS Link、Atmel SAM-ICE、Infineon DAS和ST-Link。
標簽：
keil
9.01
c51
C51
上傳時間：
2013-10-31
上傳用戶：qingdou
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NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
標簽：
2478
lpc
使用手冊
上傳時間：
2013-11-15
上傳用戶：zouxinwang
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Virtex-5, Spartan-DSP FPGAs Application Note
This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
標簽：
Spartan-DSP
Virtex
FPGAs
Ap
上傳時間：
2013-10-23
上傳用戶：raron1989
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雖然PIC都是8位的單片機，但都采用RISC（Reduced instruction Set Computing）核心結構，這有別于過去一般的CISC(Complex instruction Set Computing)結構。所謂RISC結構就是采用哈佛雙總線結構，將地址總線與數據總線分開，因此在同一個指令執行過程中，數據與地址可以同時傳送，避免了總線處理上的瓶頸。
標簽：
f877
PIC
16f
877
上傳時間：
2013-11-21
上傳用戶：tianyi223
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匯編器在微處理器的驗證和應用中舉足輕重，如何設計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統設計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發了一套匯編器系統，具有較高層次上的通用性和可移植性?！娟P鍵詞】指令集，CMDL，匯編器，開放式
Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
標簽：
開放式
匯編器
上傳時間：
2013-10-10
上傳用戶：meiguiweishi
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MCSÉ-51 Programmer's Guide and instruction Set
The information presented in this chapter is collected from the MCSÉ-51 Architectural Overview and the HardwareDescription of the 8051, 8052 and 80C51 chapters of this book. The material has been selected and rearranged toform a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the8051, 8052 and 80C51.
標簽：
Program
Eacute
MCS
51
上傳時間：
2013-11-13
上傳用戶：hj_18
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The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
標簽：
89c
c52
at
上傳時間：
2013-11-10
上傳用戶：1427796291
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With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
標簽：
NIOSII
用戶
定制
指令
上傳時間：
2013-11-07
上傳用戶：swing
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The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標簽：
Cortex-M
1850
LPC
內核微控制器
上傳時間：
2014-12-31
上傳用戶：zhuoying119
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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
標簽：
4300
LPC
ARM
雙核微控制器
上傳時間：
2013-10-28
上傳用戶：15501536189
