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intermediate-level

Introduction to the DirectX® 9 High Level Shading Language

Introduction to the DirectX® 9 High Level Shading Language

標簽： Introduction Language DirectX Shading

上傳時間： 2017-09-24

上傳用戶：ukuk
Java 3D Programming is aimed at intermediate to experienced Java developers.

Java 3D Programming is aimed at intermediate to experienced Java developers.

標簽： Java intermediate Programming experienced

上傳時間： 2013-12-04

上傳用戶：Shaikh
PXA270 design guide low level primitives

PXA270 design guide low level primitives

標簽： primitives design guide level

上傳時間： 2014-06-30

上傳用戶：yxgi5
Arduino Starter Kit Manual

Thank you for purchasing the Earthshine Design Arduino Starter Kit. You are now well on your way in your journey into the wonderful world of the Arduino and microcontroller electronics. This book will guide you, step by step, through using the Starter Kit to learn about the Arduino hardware, software and general electronics theory. Through the use of electronic projects we will take you from the level of complete beginner through to having an intermediate set of skills in using the Arduino.

標簽： Arduino Starter Manual Kit

上傳時間： 2020-06-09

上傳用戶：shancjb
3-Level Buck

Three-Level Buck CFLY Balance and Control Methodology.

標簽： CFLY

上傳時間： 2022-01-16

上傳用戶：
RISC-V 指令集手冊中文版卷 1：用戶級指令集體系結構（User-Level ISA）

RISC-V 指令集手冊卷 1：用戶級指令集體系結構（User-Level ISA）

標簽： RISC-V 指令集

上傳時間： 2022-06-18

上傳用戶：XuVshu
JPEG2000算術編碼的研究與FPGA實現(xiàn)

JPEG2000是由ISO/ITU-T組織下的IEC JTC1/SC29/WG1小組制定的下一代靜止圖像壓縮標準.與JPEG(Joint Photographic Experts Group)相比,JPEG2000能夠提供更好的數(shù)據(jù)壓縮比,并且提供了一些JPEG所不具有的功能[1].JPEG2000具有的多種特性使得它具有廣泛的應用前景.但是,JPEG2000是一個復雜編碼系統(tǒng),目前為止的軟件實現(xiàn)方案的執(zhí)行時間和所需的存儲量較大,若想將JPEG2000應用于實際中,有著較大的困難,而用硬件電路實現(xiàn)JPEG2000或者其中的某些模塊,必然能夠減少JPEG200的執(zhí)行時間,因而具有重要的意義.本文首先簡單介紹了JPEG2000這一新的靜止圖像壓縮標準,然后對算術編碼的原理及實現(xiàn)算法進行了深入的研究,并重點探討了JPEG2000中算術編碼的硬件實現(xiàn)問題,給出了一種硬件最優(yōu)化的算術編碼實現(xiàn)方案.最后使用硬件描述語言(Very High Speed Integrated Circuit Hardware Description Language,VHDL)在寄存器傳輸級(Register Transfer Level,RTL描述了該硬件最優(yōu)化的算術編碼實現(xiàn)方案,并以Altera 20K200E FPGA為基礎,在Active-HDL環(huán)境中進行了功能仿真,在Quartus Ⅱ集成開發(fā)環(huán)境下完成了綜合以及后仿真,綜合得到的最高工作時鐘頻率達45.81MHz.在相同的輸入條件下,輸出結果表明,本文設計的硬件算術編碼器與實現(xiàn)JPEG2000的軟件:Jasper[2]中的算術編碼模塊相比,處理時間縮短了30﹪左右.因而本文的研究對于JPEG2000應用于數(shù)字監(jiān)控系統(tǒng)等實際應用有著重要的意義.

標簽： JPEG 2000 FPGA 算術編碼

上傳時間： 2013-05-16

上傳用戶：671145514
The DSP Design Flow workshop provides

The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP,

標簽： workshop provides Design Flow

上傳時間： 2013-09-02

上傳用戶：joheace
Verilog Coding Style for Efficient Digital Design

In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.

標簽： Efficient Verilog Digital Coding

上傳時間： 2013-11-22

上傳用戶：han_zh
US Navy VHDL Modelling Guide

This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

標簽： Modelling Guide Navy VHDL

上傳時間： 2014-12-23

上傳用戶：xinhaoshan2016