MAXQUSBJTAGOW評估板軟件:關鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標簽： MAXQUSBJTAGOW 評估板 軟件
上傳時間： 2013-11-23
上傳用戶：truth12
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上傳時間： 2013-11-11
上傳用戶：zwei41
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2014-11-26
上傳用戶：erkuizhang
According to CIBC World Markets, Equity Research, theFlat Panel Display (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement in view quality, manufacturing efficiency,and system integration. These in turn are sustainingconsumer interest, penetration, revenue growth, and thepotential for increasing long-term profitability for industryparticipants. CIBC believes that three essential conditionsare now converging to drive the market forward
上傳時間： 2015-01-02
上傳用戶：小楓殘月
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標簽： Creating Machines Mentor State
上傳時間： 2013-11-02
上傳用戶：xauthu
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標簽： CPLD
上傳時間： 2014-12-05
上傳用戶：qazxsw
Abstract: This application note presents an overview of electronic margining and its value in detectingpotential system failures before a product ships from the factory. It is a calibration method that effectivelypredicts and allows adjustments to improve product quality. Margining also can be used to sort productsinto performance levels, allowing premium products to be sold at premium prices. We discuss thedownside of sorting and suggest alternative ways to segregate products.
上傳時間： 2014-01-22
上傳用戶：lhw888
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
Semiconductor memory, card readers, microprocessors,disc drives, piezoelectric devices and digitally based systemsfurnish transient loads that a voltage regulator mustservice. Ideally, regulator output is invariant during a loadtransient. In practice, some variation is encountered andbecomes problematic if allowable operating voltage tolerancesare exceeded. This mandates testing the regulatorand its associated support components to verify desiredperformance under transient loading conditions. Variousmethods are employable to generate transient loads, allowingobservation of regulator response
上傳時間： 2013-11-21
上傳用戶：semi1981
基于通用集成運算放大器，利用MASON公式設計了一個多功能二階通用濾波器，能同時或分別實現低通、高通和帶通濾波，也能設計成一個正交振蕩器。電路的極點頻率和品質因數能夠獨立、精確地調節。電路使用4個集成運放、2個電容和11個電阻，所有集成運放的反相端虛地。利用計算機仿真電路的通用濾波功能、極點頻率和品質因數的獨立控制和正交正弦振蕩，從而證明該濾波器正確有效。 Abstract: A new multifunctional second-order filter based on OPs was presented by MASON formula. Functions， such as high-pass， band-pass， low-pass filtering， can be realized respectively and simultaneously， and can become a quadrature oscillator by modifying resistance ratio. its pole angular frequency and quality factor can be tuned accurately and independently. The circuit presented contains four OPs， two capacitors， and eleven resistances， and inverting input of all OPs is virtual ground. its general filtering， the independent control of pole frequency and quality factor and quadrature sinusoidal oscillation were simulated by computer， and the result shows that the presented circuit is valid and effective.
上傳時間： 2013-10-09
上傳用戶：13788529953
