The use of hardware description lAnguages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
標(biāo)簽： increasingly description designing lAnguages
上傳時(shí)間： 2014-01-08
上傳用戶：小草123
gives the concepts of recursion in different lAnguages.
標(biāo)簽： different lAnguages recursion concepts
上傳時(shí)間： 2017-05-19
上傳用戶：qweqweqwe
This is a assembly lAnguages that teach how to write floppy disk subroutine. A great start for beginner who want to learn how ASM work. i got 100 for this assignment. have a look and comment
標(biāo)簽： subroutine lAnguages assembly floppy
上傳時(shí)間： 2017-06-01
上傳用戶：gououo
web development asp lAnguages easy source enterprise Invoicing System
標(biāo)簽： development enterprise Invoicing lAnguages
上傳時(shí)間： 2017-06-02
上傳用戶：baitouyu
Implementing Functional lAnguages- A Tutorial
標(biāo)簽： Implementing Functional lAnguages Tutorial
上傳時(shí)間： 2013-12-02
上傳用戶：qiao8960
An e-book about how to do 3D operations in Java (and other lAnguages). Has been very useful to me. :)
標(biāo)簽： operations lAnguages e-book useful
上傳時(shí)間： 2017-09-01
上傳用戶：清風(fēng)冷雨
本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description lAnguages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2013-10-16
上傳用戶：牛布牛
Radio Frequency Integrated Circuit Design I enjoyed reading this book for a number of reasons. One reason is that itaddresses high-speed analog design in the context of microwave issues. This isan advanced-level book, which should follow courses in basic circuits andtransmission lines. Most analog integrated circuit designers in the past workedon applications at low enough frequency that microwave issues did not arise.As a consequence, they were adept at lumped parameter circuits and often notcomfortable with circuits where waves travel in space. However, in order todesign radio frequency (RF) communications integrated circuits (IC) in thegigahertz range, one must deal with transmission lines at chip interfaces andwhere interconnections on chip are far apart. Also, impedance matching isaddressed, which is a topic that arises most often in microwave circuits. In mycareer, there has been a gap in comprehension between analog low-frequencydesigners and microwave designers. Often, similar issues were dealt with in twodifferent lAnguages. Although this book is more firmly based in lumped-elementanalog circuit design, it is nice to see that microwave knowledge is brought inwhere necessary.Too many analog circuit books in the past have concentrated first on thecircuit side rather than on basic theory behind their application in communications.The circuits usually used have evolved through experience, without asatisfying intellectual theme in describing them. Why a given circuit works bestcan be subtle, and often these circuits are chosen only through experience. Forthis reason, I am happy that the book begins first with topics that require anintellectual approach—noise, linearity and filtering, and technology issues. Iam particularly happy with how linearity is introduced (power series). In therest of the book it is then shown, with specific circuits and numerical examples,how linearity and noise issues arise.
標(biāo)簽： Rogers Radio John Freq
上傳時(shí)間： 2014-12-23
上傳用戶：han_zh
匯編器在微處理器的驗(yàn)證和應(yīng)用中舉足輕重，如何設(shè)計(jì)通用的匯編器一直是研究的熱點(diǎn)之一。本文提出了一種開(kāi)放式的匯編器系統(tǒng)設(shè)計(jì)思想，在匯編語(yǔ)言與機(jī)器語(yǔ)言間插入中間代碼CMDL（code mapping description language）語(yǔ)言，打破匯編語(yǔ)言與機(jī)器語(yǔ)言的直接映射關(guān)系，由此建立起一套描述匯編語(yǔ)言與機(jī)器語(yǔ)言的開(kāi)放式映射體系?；诖碎_(kāi)放式映射體系開(kāi)發(fā)了一套匯編器系統(tǒng)，具有較高層次上的通用性和可移植性。【關(guān)鍵詞】指令集，CMDL，匯編器，開(kāi)放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler lAnguages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler lAnguages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler lAnguages. By breaking the direct mapping relationship between assembler lAnguages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler lAnguages and machine codes to assembler lAnguages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關(guān)鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
上傳時(shí)間： 2013-10-10
上傳用戶：meiguiweishi
本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description lAnguages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時(shí)間： 2014-03-03
上傳用戶：zhtzht
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