·Phase-Locked loop Circuit Design
標簽： nbsp Phase-Locked Circuit Design
上傳時間： 2013-04-24
上傳用戶：lhc9102
Removing output capacitors saves money and boardspace. Linear Technology’s OPTI-loopTM architectureallows you to use the output capacitors of your choice andcompensate the control loop for optimum transientresponse and loop stability. Figure 1 shows the dramaticimprovement possible with the OPTI-loop architecture.With the improvement shown in Figure 1, less capacitance
上傳時間： 2013-12-15
上傳用戶：fanboynet
基于catmull-clark和loop細分的精確細分曲面曲面的法向控制程序
標簽： catmull-clark loop 分 控制
上傳時間： 2015-05-12
上傳用戶：fhzm5658
Excel spreadsheet allowing calculation of the best R-C-C component values on the PLL loop Back Filter.
標簽： spreadsheet calculation component the
上傳時間： 2014-01-14
上傳用戶：冇尾飛鉈
This zip describes a loop-back USB device port with one of the USB host ports. Includes main.html file for help.
標簽： describes USB loop-back Includes
上傳時間： 2013-11-27
上傳用戶：Divine
Toggle P1.0 by xor ing P1.0 inside of a software loop.
標簽： 1.0 software Toggle inside
上傳時間： 2015-05-27
上傳用戶：wxhwjf
Test program to loop on Successive Approximation A-to-D conversion. Allows digital codes and resulting DAC output to be viewed on scope.
標簽： Approximation Successive conversion program
上傳時間： 2015-08-07
上傳用戶：頂得柱
phase lock loop for coherent detection
標簽： detection coherent phase lock
上傳時間： 2014-01-19
上傳用戶：rocketrevenge
In this example, a task created with the configuration tool goes in a loop forever in which it spends parts of the time doing atomic operation
標簽： configuration example created forever
上傳時間： 2015-09-14
上傳用戶：qunquan
％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated signal.In this way,the phase of the ％incoming signal is locked and the signal is demodulated.This scheme ％is used in PM and FM as well. ％We will implement it by using a closed loop system.Control systems ％techniques are applied here.
標簽： phase w.r.t oscillator modulated
上傳時間： 2015-09-28
上傳用戶：zhangzhenyu
