Study on High-efficiency and Low-noise Wireless Power Transmission for Solar Power Station/Satellite
標(biāo)簽： Power High-efficiency Transmission Low-noise
上傳時(shí)間： 2015-09-24
上傳用戶：teddysha
Study on High-efficiency and Low-noise Wireless Power Transmission for Solar Power Station/Satellite
標(biāo)簽： Power High-efficiency Transmission Low-noise
上傳時(shí)間： 2013-12-19
上傳用戶：zhaiyanzhong
輸入：為需要壓縮圖象的名稱,該主程序僅能構(gòu)處理256灰度圖,讀者可以自行改編為RGB處理；ratio為壓縮比率；level為小波分解的級數(shù) 輸出:是解壓完畢的圖象數(shù)據(jù)矩陣
上傳時(shí)間： 2013-12-14
上傳用戶：diets
VHDL intermediate Level,僅供學(xué)習(xí)使用
標(biāo)簽： intermediate Level VHDL
上傳時(shí)間： 2014-12-05
上傳用戶：iswlkje
Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces between synchronous and asynchronous systems, or between synchronous systems operating from different clocks.
標(biāo)簽： synchronization highreliability highbandwidth interfaces
上傳時(shí)間： 2014-12-05
上傳用戶：l254587896
This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interconnect delays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for “l(fā)atency-insensitive” protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.
標(biāo)簽： mixed-timing low-latency interfaces first-out
上傳時(shí)間： 2015-10-08
上傳用戶：dapangxie
體現(xiàn)了lod(level of detail)算法 包括網(wǎng)格細(xì)分,空間層次
上傳時(shí)間： 2014-08-12
上傳用戶：zjf3110
This file (the project file) contains information at the project level and is used to build a single project or subproject. Other users can share the project (.dsp) file, but they should export the makefiles locally.
標(biāo)簽： project file information the
上傳時(shí)間： 2013-12-07
上傳用戶：hj_18
This Document provides the High Level Design specification for the Bootloader development and library porting for ADSP-BF533 based EZ-Kit Lite Board and STAMP Board. This document is meant to be the one of the inputs for the System Test Plan and the overall implementation of the same. This document also details the approach and assumptions made for the design
標(biāo)簽： specification development Bootloader the
上傳時(shí)間： 2015-10-14
上傳用戶：D&L37
低成本電子羅盤DataSheet規(guī)格書資料。REFERENCE DESIGN: LOW COST COMPASS； Honeywell SENSOR PRODUCTS
標(biāo)簽： DataSheet REFERENCE Honeywell PRODUCTS
上傳時(shí)間： 2014-12-06
上傳用戶：helmos
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