NEC-SIRCS-JAPAN-RC5-SAMSUNG compatible, multiprotocol infrared remote control. Replaces up to 6 existing remote controls into one. With manual learning function, LED display and/or LCD. 2V6-3V2, low power (sleep function) More protocols will be added later if needed (DENON, DAEWOO, MOTOROLA, RECS80.)
標簽： NEC-SIRCS-JAPAN-RC multiprotocol compatible Replaces
上傳時間： 2017-05-27
上傳用戶：3到15
In the last decade the processing of polygonal meshes has emerged as an active and very productive research area. This can basically be attributed to two developments: Modern geometry acquisition devices, like laser scanners and MRT, easily produce raw polygonal meshes of ever growing complexity Downstream applications like analysis tools (medical imaging), computer aided manufacturing, or numerical simulations all require high quality polygonal meshes as input. The need to bridge the gap between raw triangle soup data and high-quality polygon meshes has driven the research on ecient data structures and algorithms that directly operate on polygonal meshes rather than on a (most often not feasible) intermediate CAD representation.
標簽： processing productive the polygonal
上傳時間： 2017-06-03
上傳用戶：TF2015
This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
標簽： This microprocessor describes S3C2410A
上傳時間： 2013-11-30
上傳用戶：GavinNeko
Abstract—In this paper, we propose transform-domain algorithms to effectively classify the characteristics of blocks and estimate the strength of the blocky effect. The transform-domain algorithms require much lower computational complexity and much less memory than the spatial ones. Along with the estimated blocky strength,
標簽： transform-domain effectively algorithms Abstract
上傳時間： 2017-06-16
上傳用戶：zukfu
5800C Fm芯片資料和驅動代碼 技術特點： *國內首顆采用CMOS工藝的調頻收音機芯片； *驅動能力強，可直接驅動耳機及放大器； *功耗低，比國外先進方案還低1mA； *頻率覆蓋從76M-108M的各國調頻波段； *高度集成度，所需外圍器件數為零； *強大的LOW-IF數字音頻結構； *強大的數字信號處理技術（DSP）,實現自動頻率控制和自動增益控制； *數字自適應噪聲抑制 接受靈敏度高、音質出色、立體聲效果優異； *支持重低音，可調式電臺搜尋、柔軟靜音和混音等功能； *只需一個32.768K晶振作為參考時鐘； *支持I2C和SPI數字接口，支持I2S音頻接口，可以配合所有多媒體處理芯片； *可調去加重（50／75 us) ； *模擬和數字音量控制； *線性模擬輸出電壓； *兩線和三線控制接口模式； *封裝面積： 4×4mm，24-pin QFN
上傳時間： 2017-06-21
上傳用戶：1101055045
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput.
標簽： e.g. communication Transform important
上傳時間： 2017-06-25
上傳用戶：gxf2016
基于LPC2478硬件平臺的IAP和遠程WEB應用。 系統共分為三個部分，BOOT區，LOW區和HIGH區。可通過WEB實現對芯片的遠程IAP在線升級.
上傳時間： 2017-06-28
上傳用戶：huannan88
The LN2410SBC is a high performance single board computer based on ARM920T (MMU included). Its ultra low power consumption, various built-in IO ports and support for Linux/WinCE/RTOS make it suitable for many industry applications.
標簽： performance computer included single
上傳時間： 2013-12-08
上傳用戶：ljt101007
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2014-01-02
上傳用戶：二驅蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2017-07-05
上傳用戶：zhoujunzhen
