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Rotating shafts experience a an elliptical motion called whirl. It is important to decompose this motion into a forward and backward whil orbits. The current function makes use of two sensors to generate a bi-directional spectrogram. The method can be extended to any time-frequency distribution ％ ％ compute the forward/backward Campbell/specgtrogram ％ ％ INPUT: ％ y (n x 2) each column is measured from a different sensor ％ /////// ％ __ ％ |s1| y(:,1) ％ |__| ％ __ ％ / \ ________|/ ％ | | | s2 |/ y(:,2) ％ \____/ --------|/ ％ ％ Fs Sampling frequnecy ％ ％ OUTPUT: ％ B spectrogram/Campbel diagram ％ x x-axis coordinate vector (time or Speed) ％ y y-axis coordinate vector (frequency [Hz])
標(biāo)簽： experience elliptical decompose important
上傳時間： 2015-06-23
上傳用戶：372825274
SDL Library Documentation. The SDL library is designed to make it easy to write games that run on Linux, *BSD, MacOS, Win32 and BeOS using the various native high-performance media interfaces, (for video, audio, etc) and presenting a single source-code level API to your application. SDL is a fairly low level API, but using it, completely portable applications can be written with a great deal of flexibility.
標(biāo)簽： Documentation SDL designed Library
上傳時間： 2015-06-23
上傳用戶：nanxia
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
標(biāo)簽： 8226 Programmable Compatible In-System
上傳時間： 2015-06-27
上傳用戶：dianxin61
關(guān)于FPGA流水線設(shè)計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
reviews radar waveforms,including CW, pulsed, and LFM. High Range Resolution (HRR) waveforms and stepped frequency waveforms are also analyzed.
標(biāo)簽： waveforms Resolution including and
上傳時間： 2014-01-11
上傳用戶：jiahao131
％ This program calculates radar ranges in a jamming environment. It works ％ with both Stand-off jamming and self-screening jamming for steady and Swerling type ％ targets with frequency agility, coherent integration and standard atmosphere/rain ％ attenuation
標(biāo)簽： environment calculates Stand-off program
上傳時間： 2013-12-24
上傳用戶：sammi
本文簡要介紹了集成電路MAX038的性能，并給出了以MAX038波形產(chǎn)生器為核心具有四種輸出波形的函數(shù) 信號發(fā)生器的設(shè)計方案。用這種方法設(shè)計的信號發(fā)生器具有結(jié)構(gòu)簡單、成本低、體積小等特點，很好地滿足 了一般的實驗要求。 關(guān)鍵詞：集成電路 信號發(fā)生器 頻率 Abstract：The performance ofIC_MAX038 was introduced briefly in this paper．At the sa／ne time，a signal generator design making with integrated circuit MAX038 is provided，which can produce four kinds of waveforms output．The signal generator was of characters such as simple structur，cheap expense，small volume and SO on．The signal generator contents the demand of general experiments very wel1． Key words：Integrated circuit Signal generator Frequency
上傳時間： 2013-12-12
上傳用戶：四只眼
硬件設(shè)計指南(PDF格式)，主要包括：Low Voltage Interfaces；Grounding in Mixed Signal Systems；Digital Isolation Techniques； Power Supply Noise Reduction and Filtering； Dealing with High Speed Logic
上傳時間： 2015-08-31
上傳用戶：阿四AIR
This document describes the uIP TCP/IP stack. The uIP TCP/IP stack is an extremely small implementation of the TCP/IP protocol suite intended for embedded systems running low-end 8 or 16-bit microcon-trollers. The code size and RAM requirements of uIP is an order of magnitude smaller than other generic TCP/IP stacks today.
標(biāo)簽： stack implementat TCP describes
上傳時間： 2015-09-18
上傳用戶：zsjinju
tr1 byte "Please input the first 64-bit in hex:first - second",0dh,0ah,0 string byte "remener :use enter to tell high 32-bit from low 32-bit",0dh,0ah,0 examp1 byte "eg: 1234ecdf",0dh,0ah,0 examp2 byte " 03ab2543",0dh,0ah,0
標(biāo)簽： first byte remener Please
上傳時間： 2014-08-22
上傳用戶：huyiming139
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