The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accuracy of the algorithms implemented shows that the CORDIC functions are equivalent to the accuracy of a Pentium coprocessor.
Embedded systems for specific applications, usually in the centre, and as the core processor for the practical application of soft
Hardware systems, the hardware is the basis of the embedded operating system and platform, the software provides the necessary operational
Physical platform and communication interface, and general embedded system software, including operating systems and application software, which
Control is the core of the whole system, providing information such as HCI.
This a very simple baseband simulator for SC-FDMA system. This simulator is part of the upcoming book “Single Carrier FDMA: A New Air Interface for Long Term Evolution” (Wiley, Nov. 2008) which I co-authored with professor David J. Goodman at Polytechnic University.
The purpose of this simulator is to give some concrete idea of how SC-FDMA system works. It does lack many realistic and sophisticated features such as channel coding, time-varying fading channel model, soft decision decoding, etc. Regardless, I am hoping that it will help you understand SC-FDMA which is a fairly new development in 3GPP LTE.
In term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three
parts, and the goal of each part is described as follow.
Part I: Design a baseline JPEG software codec in C/C++ and port it to ARM core,(ARM7TDMI, ARM720T, or ARM922T.)
Part II: Make use of virtual prototype to integrate/verify the hardware and software.
Part III: Verify your soft IP in target environment.
