Generate a great circle "trajectory" from [lat1,lon1] to [lat2, lon2].
％ Resulting points will be seperated by approximately delta_ft feet.
％ By default, delta_ft = 100 feet. All lat/lon inputs & outputs are in
％ degrees.
The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed
to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6
as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up
the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are
ready for data operations
A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency
detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise reduction when compared to classicalfrequency synthesis.
AVR306串口程序例子----查詢模式
Application Note AVR306
* Polled mode driver for UART, this is the similar to the
* library default putchar() and getchar() in ICCAVR
This demonstration illustrates the application of adaptive filters to signal separation
using a structure called an adaptive line enhancer (ALE). In adaptive line
enhancement, a measured signal x(n) contains two signals, an unknown signal
of interest v(n), and a nearly-periodic noise signal eta(n). The goal is to remove
the noise signal from the measured signal to obtain the signal of interest.
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK
Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is
set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK.
Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and
used only durring TA_ISR.
ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k
simulating a convolutional encoder
allows the user to input a source code to be encoded and also input the values of the generator polynomials. It outputs the encoded data bits, where 1/n is the code rate
The ISD51_Demo project for the MSC1200 shows how to use the ISD51
In-System-Debugger with flash breakpoints or hardware breakpoints.
By default, it is configured for flash breakpoints which allow you
to set real-time breakpoints in your software. Using Flash breakpoints
has also the benefit that no special handing for the shared interrupt
vector is required, since the hardware break registers of the MSC1200
are not used at all.
