The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready for data operations
標簽： appropriately The endpoints following
上傳時間： 2013-12-02
上傳用戶：dianxin61
A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
標簽： new fractional-N synthesizer simplified
上傳時間： 2016-04-14
上傳用戶：hjshhyy
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise reduction when compared to classicalfrequency synthesis.
標簽： fractional-N transmitter bandwidth circuits
上傳時間： 2016-04-14
上傳用戶：er1219
AVR306串口程序例子----查詢模式 Application Note AVR306 * Polled mode driver for UART, this is the similar to the * library default putchar() and getchar() in ICCAVR
標簽： Application AVR 306 similar
上傳時間： 2013-12-31
上傳用戶：ryb
This demonstration illustrates the application of adaptive filters to signal separation using a structure called an adaptive line enhancer (ALE). In adaptive line enhancement, a measured signal x(n) contains two signals, an unknown signal of interest v(n), and a nearly-periodic noise signal eta(n). The goal is to remove the noise signal from the measured signal to obtain the signal of interest.
標簽： demonstration application illustrates separation
上傳時間： 2014-09-08
上傳用戶：2525775
對PL0原編譯器進行了以下的擴充：1.增加以下保留字else(elsesym), for(forsym),to(tosym),downto(downtosym),return(returnsym),[(lmparen),](rmparen) 2.增加了以下的運算符：+=(eplus),-=(eminus),++(dplus),--(dminus) 取址運算符&(radsym),指向運算符@(padsym) 3.修改單詞：修改不等號#為<> 4.擴充語句：(1)增加了else子句 (2)增加了for語句 5.增加運算：(1).++運算 (2).--運算；(3).+=運算 (4).-=運算；(5).&取址運算； (6).@指向運算； 6.增加類型：(1).增加多維數組a[i1][i2][i3]……[i(n-1)][i(n-2)][in] (2).增加指針類型(任何變量都能存放指針，但不支持指針的指針，如b:=@@a應該改寫為c:=@a,b:=@c) 7.將過程procedure擴展為函數：(1).允許定義過程時在其后加參數(var a, var b,……..,var n) (2)允許通過指針向函數形式參數傳地址；(3)允許返回值；可以用 a:=p(a,b,c….,n) 返回
標簽： downtosym returnsym elsesym downto
上傳時間： 2016-07-02
上傳用戶：saharawalker
MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and used only durring TA_ISR. ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k
標簽： Toggle Description 5.1 Contmode
上傳時間： 2014-01-04
上傳用戶：gut1234567
simulating a convolutional encoder allows the user to input a source code to be encoded and also input the values of the generator polynomials. It outputs the encoded data bits, where 1/n is the code rate
標簽： convolutional simulating encoder encoded
上傳時間： 2013-12-21
上傳用戶：253189838
The ISD51_Demo project for the MSC1200 shows how to use the ISD51 In-System-Debugger with flash breakpoints or hardware breakpoints. By default, it is configured for flash breakpoints which allow you to set real-time breakpoints in your software. Using Flash breakpoints has also the benefit that no special handing for the shared interrupt vector is required, since the hardware break registers of the MSC1200 are not used at all.
標簽： In-System-Debugger ISD the project
上傳時間： 2014-11-18
上傳用戶：dongqiangqiang
多項式擬合的MATLAB工具。只要具有以下幾個函數 POLYFITN - A general n-dimensional polynomial fitting tool POLYVALN - An evaluation tool for polynomials produced by polyfitn POLYN2SYMPOLY - A conversion tool to generate a sympoly from the results of polyfitn POLYN2SYM - A conversion tool to generate a symbolic toolbox object from the results of polyfitn
標簽： n-dimensional polynomial POLYFITN POLYVALN
上傳時間： 2014-11-30
上傳用戶：s363994250
