-
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標簽：
C16x
微控制器
輸入信號
時序圖
上傳時間：
2014-04-02
上傳用戶：han_zh
-
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯
上傳時間：
2013-11-14
上傳用戶：fdmpy
-
A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
標簽：
PICMG_COM
COMe
上傳時間：
2013-11-05
上傳用戶：Wwill
-
We all know the benefits of using FieldProgrammable Gate Arrays (FPGAs): no NRE, nominimum order quantities, and faster time-tomarket.In an ideal world, designs would never needto be changed because of design errors, but we allknow that sometimes this is necessary.
標簽：
276
WP
可編程
測試
上傳時間：
2013-11-04
上傳用戶：leixinzhuo
-
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標簽：
lpc
datasheet
2292
2294
上傳時間：
2014-12-30
上傳用戶：aysyzxzm
-
superpro 3000u 驅動
PIC16C65B@QFP44 [SA245]
PIC16C65B: Part number
QFP44: Package in QFP44
SA245: Adapter purchase number
AM29DL320GT@FBGA48 [SA642+B026]
AM29DL320GT: Part number
FBGA48: Package in FBGA48
SA642: Adapter purchase number (Top board with socket)
B026: Adapter purchase number (Bottom board, exchangable for different parts)
87C196CA@PLCC68(universal adapter) [PEP+S414T]
87C196CA: Part number
PLCC68: Package in PLCC68
universal adapter: this adapter is valid for all parts in this package
PEP: The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T)
S414T: Adapter purchase number (Universal for all parts in this package)
S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)]
S71PL127J80B: Part number
FBGA64: Package in FBGA64
special adapter: this adapter is valid for this
標簽：
superpro
3000u
驅動
編程器軟件
上傳時間：
2013-10-23
上傳用戶：Avoid98
-
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯
上傳時間：
2013-11-23
上傳用戶：shen_dafa
-
Logger iButton devices have gained a lot of popularity with researchers. Although free evaluation software is easy to use and welldocumented, the choices and inputs that need to be made can sometimes be challenging. This application note explains technicalterms that are common with temperature logger iButtons and how they relate to each other. Additionally, it presents an algorithm tohelp users choose the necessary input parameters, including the sample rate based on a user's needs and the available memory tostore the data.
標簽：
參數
溫度記錄儀
上傳時間：
2013-11-16
上傳用戶：xywhw1
-
superpro 3000u 驅動
PIC16C65B@QFP44 [SA245]
PIC16C65B: Part number
QFP44: Package in QFP44
SA245: Adapter purchase number
AM29DL320GT@FBGA48 [SA642+B026]
AM29DL320GT: Part number
FBGA48: Package in FBGA48
SA642: Adapter purchase number (Top board with socket)
B026: Adapter purchase number (Bottom board, exchangable for different parts)
87C196CA@PLCC68(universal adapter) [PEP+S414T]
87C196CA: Part number
PLCC68: Package in PLCC68
universal adapter: this adapter is valid for all parts in this package
PEP: The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T)
S414T: Adapter purchase number (Universal for all parts in this package)
S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)]
S71PL127J80B: Part number
FBGA64: Package in FBGA64
special adapter: this adapter is valid for this
標簽：
superpro
3000u
驅動
編程器軟件
上傳時間：
2014-03-27
上傳用戶：ippler8
-
This a separate release of the OpenSS7 X/Open XTI/TLI library, TLI modules (timod, tirdwr) and the INET driver (inet) that provides Unix98 compatible interface to Linux NET4 TCP/IP stacks, and all the necessary manpages and other documentation. Although these components are contained in our LiS and Linux Fast-STREAMS releases, this tarball configures, builds and installs these components separate from those releases.
標簽：
TLI
the
separate
OpenSS7
上傳時間：
2015-03-12
上傳用戶：mikesering
