Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
Power conversion by virtue of its basic role produces harmonics due to theslicing of either voltages or currents. To a large extent the pollution in theutility supply and the deterioration of the power quality has been generatedor created by non-linear converters. It is therefore ironic that power convertersshould now be used to clean up the pollution that they helped to create inthe first place.In a utility system, it is desirable to prevent harmonic currents (which resultin EMI and resonance problems) and limit reactive power flows (whichresult in transmission losses).Traditionally, shunt passive filters, comprised of tuned LC elements andcapacitor banks, were used to filter the harmonics and to compensate forreactive current due to non-linear loads. However, in practical applicationsthese methods have many disadvantages.
交流瓦特/瓦特小時，乏爾/乏爾小時轉換器 特點： 精確度0.25%滿刻度 多種輸入,輸出選擇 輸入與輸出絕緣耐壓2仟伏特/1分鐘 沖擊電壓測試5仟伏特(1.2x50us) 突波電壓測試2.5仟伏特(0.25ms/1MHz) (IEC255-4) 尺寸小，穩定性高 主要規格： 精確度: 0.25% F.S. (23 ±5℃) 輸入負載: <0.2VA (Voltage) <0.2VA (Current) 最大過載能力: Current related input:3 x rated continuous 10 x rated 30 sec. ,25 x rated 3sec. 50 x rated 1sec. Voltage related input:maximum 2 x rated continuous 輸出反應速度: < 250ms(0~90%) 輸出負載能力: < 10mA for voltage mode < 10V for current mode 輸出之漣波 : < 0.1% F.S. 脈波輸出型態: Photocouple of open collector (max.30V/40mA) 歸零調整范圍: 0~±5% F.S. 最大值調整范圍: 0~±10% F.S. 溫度系數: 100ppm/℃ (0~50℃) 隔離特性: Input/Output/Power/Case 絕緣阻抗: >100Mohm with 500V DC 絕緣耐壓能力: 2KVac/1 min. (input/output/power/case) 突波測試: ANSI C37.90a/1974,DIN-IEC 255-4 impulse voltage 5KV(1.2x50us) 使用環境條件: -20~60℃(20 to 90% RH non-condensed) 存放環境條件: -30~70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
Power over Ethernet (PoE) is a new development thatallows for the delivery of power to Ethernet-based devicesvia standard Ethernet CAT5 cable, precluding the need forwall adapters or other external power sources. The PoEspecification defines a hardware detection protocol wherePower Sourcing Equipment (PSE) is able to identify PoEPowered Devices (PDs), thus allowing full backwardscompatibility with non-PoE-aware (legacy) Ethernetdevices.
DC/DC 升壓IC：The FP6291 is a current mode boost DC-DC converter. Its PWM circuitry with built-in 0.25 Ω
power MOSFET make this regulator highly power efficient. The internal compensation network also
minimizes as much as 6 external component counts. The non-inverting input of error amplifier connects
to a 0.6V precision reference voltage and internal soft-start function can reduce the inrush current.
The FP6291 is available in the SOT23-6L package and provides space-saving PCB for the application fields.
A frequent requirement in systems involves drivinganalog signals into non-linear or reactive loads. Cables,transformers, actuators, motors and sample-hold circuitsare examples where the ability to drive diffi cult loads isrequired. Although several power buffer amplifi ers areavailable, none have been optimized for driving diffi cultloads.
This application report discusses the design of non-invasive optical plethysmographyalso called as pulsoximeter using the MSP430FG437 Microcontroller (MCU). Thepulsoximeter consists of a peripheral probe combined with the MCU displaying theoxygen saturation and pulse rate on a LCD glass. The same sensor is used for bothheart-rate detection and pulsoximetering in this application. The probe is placed on aperipheral point of the body such as a finger tip, ear lobe or the nose. The probeincludes two light emitting diodes (LEDs), one in the visible red spectrum (660nm) andthe other in the infrared spectrum (940nm). The percentage of oxygen in the body isworked by measuring the intensity from each frequency of light after it transmitsthrough the body and then calculating the ratio between these two intensities.
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。
Abstract:
In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
