Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： Virtex FPGA PCB 設(shè)計(jì)手冊(cè)
上傳時(shí)間： 2014-01-13
上傳用戶：竺羽翎2222
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時(shí)間： 2013-10-22
上傳用戶：李哈哈哈
USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
上傳時(shí)間： 2013-10-12
上傳用戶：windgate
ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時(shí)間： 2013-11-13
上傳用戶：takako_yang
UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計(jì)
上傳時(shí)間： 2013-11-07
上傳用戶：jasson5678
The XPS Ethernetlite peripheral does not provide any mechanism to access the Ethernet PHYregisters. These registers are used to configure auto negotiation parameters and to obtain PHYstatus. This application note provides reference systems and associated software to accessPHY registers by connecting the serial management bus signals MDC and MDIO to GPIOswhich the software controls directly.
上傳時(shí)間： 2013-10-17
上傳用戶：JamesB
User ManualRev. 1.2SmartRF® CC2420DK: Packet Sniffer for IEEE 802.15.4 and ZigBee Table of contents1 INTRODUCTION...............................................................................................31.1 HARDWARE PLATFORM.......................................................................................31.2 SOFTWARE.........................................................................................................32 USER INTERFACE..........................................................................................42.1 MENUS AND TOOLBARS.......................................................................................62.2 SETUP................................................................................................................62.3 SELECT FIELDS...................................................................................................72.3.1 Tips............................................................................................................72.4 PACKET DETAILS.................................................................................................72.5 ADDRESS BOOK..................................................................................................92.5.1 Tips............................................................................................................92.6 DISPLAY FILTER................................................................................................102.7 TIME LINE.........................................................................................................103 HELP....................................................................................................................114 TROUBLESHOOTING..................................................................................125 GENERAL INFORMATION........................................................................135.1 DOCUMENT HISTORY........................................................................................135.2 DISCLAIMER......................................................................................................135.3 TRADEMARKS...................................................................................................136 ADDRESS INFORMATION........................................................................14
標(biāo)簽： 數(shù)據(jù) 分析儀 說(shuō)明書(shū)
上傳時(shí)間： 2014-01-14
上傳用戶：zhangyi99104144
protel99電子線路圖繪圖工具.Protel99SE是Protel公司近10年來(lái)致力于Windows平臺(tái)開(kāi)發(fā)的最新結(jié)晶，能實(shí)現(xiàn)從電學(xué)概念設(shè)計(jì)到輸出物理生產(chǎn)數(shù)據(jù)，以及這之間的所有分析、驗(yàn)證和設(shè)計(jì)數(shù)據(jù)管理。因而今天的Protel最新產(chǎn)品已不是單純的PCB（印制電路板）設(shè)計(jì)工具，而是一個(gè)系統(tǒng)工具，覆蓋了以PCB為核心的整個(gè)物理設(shè)計(jì)。 最新版本的Protel軟件可以毫無(wú)障礙地讀Orcad、Pads、Accel(PCAD)等知名EDA公司設(shè)計(jì)文件，以便用戶順利過(guò)渡到新的EDA平臺(tái)。 Protel99 SE共分5個(gè)模塊，分別是原理圖設(shè)計(jì)、PCB設(shè)計(jì)（包含信號(hào)完整性分析）、自動(dòng)布線器、原理圖混合信號(hào)仿真、PLD設(shè)計(jì)。 以下介紹一些Protel99SE的部分最新功能： ◆可生成30多種格式的電氣連接網(wǎng)絡(luò)表； ◆強(qiáng)大的全局編輯功能； ◆在原理圖中選擇一級(jí)器件，PCB中同樣的器件也將被選中； ◆同時(shí)運(yùn)行原理圖和PCB，在打開(kāi)的原理圖和PCB圖間允許雙向交叉查找元器件、引腳、網(wǎng)絡(luò) ◆既可以進(jìn)行正向注釋元器件標(biāo)號(hào)（由原理圖到PCB），也可以進(jìn)行反向注釋（由PCB到原理圖），以保持電氣原理圖和PCB在設(shè)計(jì)上的一致性； ◆滿足國(guó)際化設(shè)計(jì)要求（包括國(guó)標(biāo)標(biāo)題欄輸出，GB4728國(guó)標(biāo)庫(kù)）； * 方便易用的數(shù)模混合仿真（兼容SPICE 3f5）； ◆支持用CUPL語(yǔ)言和原理圖設(shè)計(jì)PLD，生成標(biāo)準(zhǔn)的JED下載文件； * PCB可設(shè)計(jì)32個(gè)信號(hào)層，16個(gè)電源-地層和16個(gè)機(jī)加工層； ◆強(qiáng)大的“規(guī)則驅(qū)動(dòng)”設(shè)計(jì)環(huán)境，符合在線的和批處理的設(shè)計(jì)規(guī)則檢查； ◆智能覆銅功能，覆鈾可以自動(dòng)重鋪； ◆提供大量的工業(yè)化標(biāo)準(zhǔn)電路板做為設(shè)計(jì)模版； ◆放置漢字功能； ◆可以輸入和輸出DXF、DWG格式文件，實(shí)現(xiàn)和AutoCAD等軟件的數(shù)據(jù)交換； ◆智能封裝導(dǎo)航（對(duì)于建立復(fù)雜的PGA、BGA封裝很有用）； ◆方便的打印預(yù)覽功能，不用修改PCB文件就可以直接控制打印結(jié)果； ◆獨(dú)特的3D顯示可以在制板之前看到裝配事物的效果； ◆強(qiáng)大的CAM處理使您輕松實(shí)現(xiàn)輸出光繪文件、材料清單、鉆孔文件、貼片機(jī)文件、測(cè)試點(diǎn)報(bào)告等； ◆經(jīng)過(guò)充分驗(yàn)證的傳輸線特性和仿真精確計(jì)算的算法，信號(hào)完整性分析直接從PCB啟動(dòng)； ◆反射和串?dāng)_仿真的波形顯示結(jié)果與便利的測(cè)量工具相結(jié)合； ◆專家導(dǎo)航幫您解決信號(hào)完整性問(wèn)題。
標(biāo)簽： protel setup 99 電子線路圖
上傳時(shí)間： 2013-10-14
上傳用戶：hanwudadi
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時(shí)間： 2013-10-24
上傳用戶：s藍(lán)莓汁
The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8! Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects! This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever. Not just what to d why to do it! Use labview to build your own virtual workbench Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more Learn the "art" and best practices of effective labview development NEW: Streamline development with labview Express VIs NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
標(biāo)簽： Everyone LabVIEW for 英文
上傳時(shí)間： 2013-10-14
上傳用戶：shawvi
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