The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標(biāo)簽： Cortex-M 1850 LPC 內(nèi)核微控制器
上傳時(shí)間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時(shí)間： 2013-10-28
上傳用戶：15501536189
本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè)：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時(shí)間： 2013-11-12
上傳用戶：18711024007
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
This document discusses recommended practices and style for programmers using the C language in the Flight Dynamics Division environment. Guidelines are based on generally recommended software engineering techniques, industry resources, and local convention. The Guide offers preferred solutions to common C programming issues and illustrates through examples of C code.
標(biāo)簽： recommended programmers discusses practices
上傳時(shí)間： 2015-07-19
上傳用戶：jcljkh
JavaTV Program source code Need to play Windows Media files and streams, mpeg4 video or DVDs in java? Access WDM capture devices? Control a firewire DVCam? Then maybe this can help you. dsj is an ongoing project to provide a java wrapper around Microsoft s DirectShow API. It offers a set of high level classes that give java easy access to functionality widely missed by java programmers and also lets you dive deeper into the interiors of Windows core api for 2D media. On the java side dsj tries to keep things open as possible - you may use it standalone or let it feed data into JMF or other APIs.
標(biāo)簽： Program Windows streams JavaTV
上傳時(shí)間： 2013-12-17
上傳用戶：TF2015
C++ Standard Library provides a set of common classes and interfaces that greatly extend the core C++ language. The library, however, is not self-explanatory. To make full use of its components-and to benefit from their power-you need a resource that does far more than list the classes and their functions. The C++ Standard Library not only provides comprehensive documentation of each library component, it also offers clearly written explanations of complex concepts, describes the practical programming details needed for effective use, and gives example after example of working code.
標(biāo)簽： interfaces Standard provides Library
上傳時(shí)間： 2014-03-01
上傳用戶：lizhizheng88
This book presents an insightful view of XML that places this emerging technology in the context of the ongoing Web revolution. Written for business and technical professionals, this book revals the true value of XML for distributed information systems. It explains how XML is transforming the way organizations manage data and build software systems details the opportunities the language offers for organizatoins that understand tis significance and potential impact and explains how XML and Web services reflect a fundamental shift in software construction-from monolithic applications to software based on the composition of simple parts.
標(biāo)簽： insightful technology presents emerging
上傳時(shí)間： 2015-09-24
上傳用戶：思琦琦
PeerSec Networks MatrixSSL?is an embedded SSL implementation designed for small footprint applications and devices. PeerSec Networks offers a fully supported, commercial version as well as an open source version that is available for download. PeerSec MatrixSSL allows secure management of remote devices. Several secure embedded Web servers also use MatrixSSL for their encryption layer.
標(biāo)簽： implementation applicatio MatrixSSL footprint
上傳時(shí)間： 2014-01-18
上傳用戶：561596
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each generator offers macro and micro-architecture selections that allow full customization of the generated model to the target application requirements.
標(biāo)簽： AccelWare generators introduce exercise
上傳時(shí)間： 2013-12-16
上傳用戶：2467478207
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