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The XML Toolbox converts MATLAB data types (such as double, char, struct, complex, sparse, logical) of any level of nesting to XML format and vice versa.
For example,
>> project.name = MyProject
>> project.id = 1234
>> project.param.a = 3.1415
>> project.param.b = 42
becomes with str=xml_format(project, off )
"<project>
<name>MyProject</name>
<id>1234</id>
<param>
<a>3.1415</a>
<b>42</b>
</param>
</project>"
On the other hand, if an XML string XStr is given, this can be converted easily to a MATLAB data type or structure V with the command V=xml_parse(XStr).
標簽：
converts
Toolbox
complex
logical
上傳時間：
2016-02-12
上傳用戶：a673761058
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This application creates an USB HID (Human-Interface Device) keyboard on a host computer. Pressing any of the buttons on the board outputs characters or special keys on the host side
標簽：
Human-Interface
application
Pressing
computer
上傳時間：
2014-01-04
上傳用戶：曹云鵬
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PenguinCards is a java-based card game. You can either play against computer or another player. On the board, there are card pairs and your aim is to find out these card pairs. The one who finds out more card pairs is the winner. Have fun!
標簽：
PenguinCards
java-based
computer
against
上傳時間：
2013-12-17
上傳用戶：xfbs821
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特點： 精確度0.1%滿刻度 可作各式數(shù)學演算式功能如:A+B/A-B/AxB/A/B/A&B(Hi or Lo)/|A|/ 16 BIT類比輸出功能 輸入與輸出絕緣耐壓2仟伏特/1分鐘(input/output/power) 寬范圍交直流兩用電源設計 尺寸小,穩(wěn)定性高
標簽：
微電腦
數(shù)學演算
隔離傳送器
上傳時間：
2014-12-23
上傳用戶：ydd3625
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特點(FEATURES) 精確度0.1%滿刻度 (Accuracy 0.1%F.S.) 可作各式數(shù)學演算式功能如:A+B/A-B/AxB/A/B/A&B(Hi or Lo)/|A| (Math functioA+B/A-B/AxB/A/B/A&B(Hi&Lo)/|A|/etc.....) 16 BIT 類比輸出功能(16 bit DAC isolating analog output function) 輸入/輸出1/輸出2絕緣耐壓2仟伏特/1分鐘(Dielectric strength 2KVac/1min. (input/output1/output2/power)) 寬范圍交直流兩用電源設計(Wide input range for auxiliary power) 尺寸小,穩(wěn)定性高(Dimension small and High stability)
標簽：
微電腦
數(shù)學演算
輸出
隔離傳送器
上傳時間：
2013-11-24
上傳用戶：541657925
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Multiple-voltage electronics systems often requirecomplex supply voltage tracking or sequencing, whichif not met, can result in system faults or even permanentfailures in the fi eld. The design diffi culties in meetingthese requirements are often compounded in distributedpowerarchitectures where point-of-load (POL) DC/DCconverters or linear regulators are scattered across PCboard space, sometimes on different board planes. Theproblem is that power supply circuitry is often the lastcircuitry to be designed into the board, and it must beshoehorned into whatever little board real estate is left.Often, a simple, drop-in, fl exible solution is needed tomeet these requirements.
標簽：
負載點電路
電源電壓
排序
上傳時間：
2013-10-08
上傳用戶：15071087253
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/*--------- 8051內(nèi)核特殊功能寄存器 -------------*/
sfr ACC = 0xE0; //累加器
sfr B = 0xF0; //B 寄存器
sfr PSW = 0xD0; //程序狀態(tài)字寄存器
sbit CY = PSW^7; //進位標志位
sbit AC = PSW^6; //輔助進位標志位
sbit F0 = PSW^5; //用戶標志位0
sbit RS1 = PSW^4; //工作寄存器組選擇控制位
sbit RS0 = PSW^3; //工作寄存器組選擇控制位
sbit OV = PSW^2; //溢出標志位
sbit F1 = PSW^1; //用戶標志位1
sbit P = PSW^0; //奇偶標志位
sfr SP = 0x81; //堆棧指針寄存器
sfr DPL = 0x82; //數(shù)據(jù)指針0低字節(jié)
sfr DPH = 0x83; //數(shù)據(jù)指針0高字節(jié)
/*------------ 系統(tǒng)管理特殊功能寄存器 -------------*/
sfr PCON = 0x87; //電源控制寄存器
sfr AUXR = 0x8E; //輔助寄存器
sfr AUXR1 = 0xA2; //輔助寄存器1
sfr WAKE_CLKO = 0x8F; //時鐘輸出和喚醒控制寄存器
sfr CLK_DIV = 0x97; //時鐘分頻控制寄存器
sfr BUS_SPEED = 0xA1; //總線速度控制寄存器
/*----------- 中斷控制特殊功能寄存器 --------------*/
sfr IE = 0xA8; //中斷允許寄存器
sbit EA = IE^7; //總中斷允許位
sbit ELVD = IE^6; //低電壓檢測中斷控制位
8051
標簽：
80C51
特殊功能寄存器
地址
上傳時間：
2013-10-30
上傳用戶：yxgi5
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TLC2543是TI公司的12位串行模數(shù)轉(zhuǎn)換器，使用開關電容逐次逼近技術完成A/D轉(zhuǎn)換過程。由于是串行輸入結構，能夠節(jié)省51系列單片機I/O資源；且價格適中，分辨率較高，因此在儀器儀表中有較為廣泛的應用。
TLC2543的特點
（1）12位分辯率A/D轉(zhuǎn)換器；
（2）在工作溫度范圍內(nèi)10μs轉(zhuǎn)換時間；
（3）11個模擬輸入通道；
（4）3路內(nèi)置自測試方式；
（5）采樣率為66kbps；
（6）線性誤差±1LSBmax；
（7）有轉(zhuǎn)換結束輸出EOC；
（8）具有單、雙極性輸出；
（9）可編程的MSB或LSB前導；
（10）可編程輸出數(shù)據(jù)長度。
TLC2543的引腳排列及說明
TLC2543有兩種封裝形式：DB、DW或N封裝以及FN封裝，這兩種封裝的引腳排列如圖1，引腳說明見表1
TLC2543電路圖和程序欣賞
#include<reg52.h>
#include<intrins.h>
#define uchar unsigned char
#define uint unsigned int
sbit clock=P1^0; sbit d_in=P1^1;
sbit d_out=P1^2;
sbit _cs=P1^3;
uchar a1,b1,c1,d1;
float sum,sum1;
double sum_final1;
double sum_final;
uchar duan[]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f};
uchar wei[]={0xf7,0xfb,0xfd,0xfe};
void delay(unsigned char b) //50us
{
unsigned char a;
for(;b>0;b--)
for(a=22;a>0;a--);
}
void display(uchar a,uchar b,uchar c,uchar d)
{
P0=duan[a]|0x80;
P2=wei[0];
delay(5);
P2=0xff;
P0=duan[b];
P2=wei[1];
delay(5);
P2=0xff;
P0=duan[c];
P2=wei[2];
delay(5);
P2=0xff;
P0=duan[d];
P2=wei[3];
delay(5);
P2=0xff;
}
uint read(uchar port)
{
uchar i,al=0,ah=0;
unsigned long ad;
clock=0;
_cs=0;
port<<=4;
for(i=0;i<4;i++)
{
d_in=port&0x80;
clock=1;
clock=0;
port<<=1;
}
d_in=0;
for(i=0;i<8;i++)
{
clock=1;
clock=0;
}
_cs=1;
delay(5);
_cs=0;
for(i=0;i<4;i++)
{
clock=1;
ah<<=1;
if(d_out)ah|=0x01;
clock=0;
}
for(i=0;i<8;i++)
{
clock=1;
al<<=1;
if(d_out) al|=0x01;
clock=0;
}
_cs=1;
ad=(uint)ah;
ad<<=8;
ad|=al;
return(ad);
}
void main()
{
uchar j;
sum=0;sum1=0;
sum_final=0;
sum_final1=0;
while(1)
{
for(j=0;j<128;j++)
{
sum1+=read(1);
display(a1,b1,c1,d1);
}
sum=sum1/128;
sum1=0;
sum_final1=(sum/4095)*5;
sum_final=sum_final1*1000;
a1=(int)sum_final/1000;
b1=(int)sum_final%1000/100;
c1=(int)sum_final%1000%100/10;
d1=(int)sum_final%10;
display(a1,b1,c1,d1);
}
}
標簽：
2543
TLC
上傳時間：
2013-11-19
上傳用戶：shen1230
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#include<iom16v.h>
#include<macros.h>
#define uint unsigned int
#define uchar unsigned char
uint a,b,c,d=0;
void delay(c)
{ for for(a=0;a<c;a++)
for(b=0;b<12;b++);
};
uchar tab[]={
0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90,
標簽：
AVR
單片機
數(shù)碼管
上傳時間：
2013-10-21
上傳用戶：13788529953
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This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯(lián)
上傳時間：
2013-11-14
上傳用戶：fdmpy
