可以用此工具將PROTEL，ORCAD等PCB資料，轉(zhuǎn)換成PADS所需格式。
上傳時(shí)間： 2013-10-19
上傳用戶(hù)：changeboy
PCB 原理圖
標(biāo)簽： OrCAD PADS 實(shí)現(xiàn)方法
上傳時(shí)間： 2013-10-29
上傳用戶(hù)：dudu121
HIGH SPEED 8051 μC CORE - Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz System Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (256 + 4k) - 64k Bytes In-System Programmable FLASH Program Memory - External Parallel Data Memory Interface – up to 5Mbytes/sec DIGITAL PERIPHERALS - 64 Port I/O; All are 5V tolerant - Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules - 5 General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE ........................ 2.7V to 3.6V - Typical Operating Current: 10mA @ 25MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP (64-Pin Version Available) Temperature Range: –40°C to +85°C
標(biāo)簽： C8051F020
上傳時(shí)間： 2013-10-12
上傳用戶(hù)：lalalal
Digitemp Junior – An RS-232 Port-Powered Digital Thermometer Digitemp Jr. is a device that is designed to measure and report ambient temperature. When connected to an RS-232 port on any PC, it will periodically measure and report in ASCII form the ambient temperature in degrees Celsius. These temperature readings can be monitored with any terminal program. If the terminal program supports capture to disk, the temperature readings can be saved to disk for further analysis with a spreadsheet program or other data analysis tool. The simple ASCII output format of Digitemp Jr. makes it rel- atively easy to write custom software for receiving, recording, and analyzing ambient temperature data. Best of all, Digitemp Jr. requires no external power sup- plies or batteries. It is powered directly by the RS-232 port.
標(biāo)簽： Microchip 232 PIC RS
上傳時(shí)間： 2013-10-21
上傳用戶(hù)：baitouyu
Digitemp Jr. is a device that is designed to measure and report ambient temperature. When connected to an RS-232 port on any PC, it will periodically measure and report in ASCII form the ambient temperature in degrees Celsius. These temperature readings can be monitored with any terminal program. If the terminal program supports capture to disk, the temperature readings can be saved to disk for further analysis with a spreadsheet program or other data analysis tool. The simple ASCII output format of Digitemp Jr. makes it relatively easy to write custom software for receiving, recording, and analyzing ambient temperature data. Best of all, Digitemp Jr. requires no external power supplies or batteries. It is powered directly by the RS-232 port.
上傳時(shí)間： 2013-10-20
上傳用戶(hù)：Maple
SPMC65系列單片機(jī)編程指南(中文版):SPMC65X系列是由凌陽(yáng)公司設(shè)計(jì)開(kāi)發(fā)的8位微控制器。每款芯片都獨(dú)具特色，同時(shí)凌陽(yáng)公司還開(kāi)發(fā)了一款仿真芯片ECMC653，專(zhuān)門(mén)用于SPMC65X系列的仿真。采用 SPMC65 CPU 核，凌陽(yáng)公司新開(kāi)發(fā)了功能強(qiáng)大的8位SPMC65系列CPU。該系列CPU 具有可編程的通用I/O端口、不同大小的ROM 和RAM 區(qū)、8位/16位定時(shí)/計(jì)數(shù)器、強(qiáng)大的CCP (Capture/Compare/PWM)功能模塊和看門(mén)狗復(fù)位電路等。并采用先進(jìn)的微米制造工藝，保證了產(chǎn)品高的電磁兼容性和可靠性。除此之外，部分SPMC65X系列芯片具備高吸入電流和慢速輸出的端口、豐富的外部中斷源、低電壓復(fù)位、ADC、PWM、標(biāo)準(zhǔn)通訊接口和多種時(shí)鐘選擇。SPMC65X系列芯片適用于通用工控場(chǎng)合、計(jì)算機(jī)外圍控制和家電等。ECMC653采用8位SPMC65 CPU 核，具有928字節(jié)的RAM 和16k字節(jié)的ROM。同時(shí)還集成了1個(gè)時(shí)基、1個(gè)看門(mén)狗定時(shí)器、6個(gè)16位定時(shí)/計(jì)數(shù)器和9通道的ADC。為了降低整個(gè)仿真板的成本，該芯片還配有一個(gè)OTP ROM 的串行可編程接口。此外，為了幫助用戶(hù)加快程序的調(diào)試，并發(fā)現(xiàn)程序中隱藏的錯(cuò)誤，該芯片內(nèi)部專(zhuān)門(mén)有一RAM區(qū)域用于記錄程序最近一段時(shí)間執(zhí)行的指令，用戶(hù)可以從中了解到程序是否正確執(zhí)行。
標(biāo)簽： SPMC 65 單片機(jī) 編程指南
上傳時(shí)間： 2013-11-01
上傳用戶(hù)：Jesse_嘉偉
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶(hù)：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽： C16x 微控制器 輸入信號(hào) 時(shí)序圖
上傳時(shí)間： 2014-04-02
上傳用戶(hù)：han_zh
交通燈控制板用戶(hù)手冊(cè)、交通燈源代碼、交通燈電路原理圖(用Orcad打開(kāi))、交通燈電路原理圖(用PDF打開(kāi))、交通燈PCB圖
標(biāo)簽： 交通燈 控制板 用戶(hù)手冊(cè)
上傳時(shí)間： 2013-10-13
上傳用戶(hù)：manlian
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶(hù)：fdmpy
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