To describe pattern Recognition using Machine Learning Method. It is good for one who want to learn machine learning.
標(biāo)簽： pattern recognition ML machine learning
上傳時(shí)間： 2016-04-14
上傳用戶：shishi
pattern recognition has its origins in engineering, whereas machine learning grew out of computer science. However, these activities can be viewed as two facets of the same field, and together they have undergone substantial development over the past ten years. In particular, Bayesian methods have grown from a specialist niche to become mainstream, while graphical models have emerged as a general framework for describing and applying probabilistic models. Also, the practical applicability of Bayesian methods has been greatly enhanced through the development of a range of approximate inference algorithms such as variational Bayes and expectation propa- gation. Similarly, new models based on kernels have had significant impact on both algorithms and applications.
標(biāo)簽： Bishop-pattern-Recognition-and-Ma chine-Learning
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
The Reactor design pattern handles service requests that are delivered concurrently to an application by one or more clients. Each service in an application may consist of serveral methods and is represented by a separate event handler that is responsible for dispatching service-specific requests.
上傳時(shí)間： 2013-10-15
上傳用戶：libinxny
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
標(biāo)簽： RocketIO Virtex XAPP 713
上傳時(shí)間： 2013-12-25
上傳用戶：jkhjkh1982
SPLASH is a c++ class library that implements many of the Perl constructs and data types, including extensive regex regular expression pattern matching. For those not familiar with Perl, it is an excellent scripting language by Larry Wall and is available for most platforms. This Class library provides List, String, Regular Expression, and text manipulation handling capabilities based on those provided in Perl
標(biāo)簽： implements constructs including library
上傳時(shí)間： 2013-12-07
上傳用戶：1583060504
ATmega8 taillight circuitAn assembly language program that generates 5 different static patterns with switching from pattern-to-pattern controlled by the depression of one push-button switch (S2).
標(biāo)簽： taillight circuitAn generates different
上傳時(shí)間： 2014-01-12
上傳用戶：wanghui2438
This code is to estimate the parameter of model of Mixture Gauss which is popular model used in pattern classification . JAVA 寫的估計(jì)復(fù)合高斯模型中的參數(shù)
標(biāo)簽： model parameter estimate Mixture
上傳時(shí)間： 2015-04-10
上傳用戶：kikye
this is a trade sale system realized by java. It can run some easy functions and has a good design pattern CVS. A good project to learn CVS.
標(biāo)簽： functions realized design system
上傳時(shí)間： 2015-04-17
上傳用戶：sz_hjbf
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