pg059-axi-interconnect
標(biāo)簽： axi-interconnect 059 pgpg059-axi-interconnect
上傳時(shí)間： 2016-05-04
上傳用戶：BLOSSOM93
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
axi協(xié)議的文檔，介紹AMBA Advanced eXtensible Interface (AXI) Protocol
上傳時(shí)間： 2013-04-24
上傳用戶：tongda
目的是利用嵌入在Xilinx FPGA中的MicroBlaze核實(shí)現(xiàn)基于AXI總線的雙核嵌入式系統(tǒng)設(shè)計(jì)以及共享實(shí)現(xiàn)LED燈的時(shí)控.
標(biāo)簽： MicroBlaze SoPC AXI 總線
上傳時(shí)間： 2014-12-30
上傳用戶：stewart·
AXI Reference Guide (AXI).pdf
上傳時(shí)間： 2013-10-29
上傳用戶：libinxny
AXI Bus Functional Model v1.1 Product Brief.pdf
標(biāo)簽： AXI 1.1 總線 產(chǎn)品簡介
上傳時(shí)間： 2015-01-01
上傳用戶：kbnswdifs
Rapid IO Interconnect Specification Physical Layer.
標(biāo)簽： Specification Interconnect Physical Rapid
上傳時(shí)間： 2014-01-16
上傳用戶：極客
外圍組件接口技術(shù)（Peripheral Component Interconnect PCI）是一種新型的高帶寬、處理器無關(guān)的總線系統(tǒng)。它既可以作為中間層的總線也可以作為周邊總線系統(tǒng)使用。與其他普通總線規(guī)范想對照，PCI 總線為高速I/O設(shè)備提供了更好的支持（比如圖形適配器、網(wǎng)絡(luò)接口控制器、磁盤控制器，等等）。現(xiàn)行的標(biāo)準(zhǔn)允許在33Mhz下使用64根數(shù)據(jù)線，純傳輸速率可達(dá)2.11Gbps。但是PCI吸引人的地方不在于它的高速度，它適應(yīng)了現(xiàn)代I/O設(shè)備對系統(tǒng)的要求，并且只需要很少的芯片就可以實(shí)現(xiàn)并支持其他總線系統(tǒng)。
標(biāo)簽： Interconnect Peripheral Component PCI
上傳時(shí)間： 2017-01-17
上傳用戶：qb1993225
Local interconnect network LIN (bus interface)
標(biāo)簽： interconnect interface network Local
上傳時(shí)間： 2017-08-06
上傳用戶：youlongjian0
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