This book is intended for the graduate or advanced undergraduate
engineer. The primary motivation for developing the text was to present a
complete tutorial of phase-locked loops with a consistent notation. I believe
this is critical for the practicing engineer who uses the text as a self-study
guide.
This document describes how to switch to and program the unisersal serial bus (USB)
analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example
assembly programs for programming and switching to and from the APLL are also
provided in the attached zip file. It is assumed that the reader is familiar with the use
and operation of the C5506/C5507/C5509A USB digital phase-locked loop (DPLL) and
C55x™ Digital Signal Processor (DSP) IDLE procedures.
The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both integer-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthesizer.This application note compares the MAX2870 and ADF4350 registers andloop filter design in detail. Users who already familiar with ADF4350 canuse this application note as a quick design reference.
Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) products use crystal oscillators to generate areference for the phase-locked loop (PLL)-based local oscillator (LO). This tutorial provides a basic description of theISM-RF Crystal Calculator, which can be used to calculate various impacts on crystal frequency accuracy and startupmargin for such an LO.
Many applications require a clock signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another clock. This type of clock circuit is important in
Telecommunication, satellite links and set-top boxes allrequire tuning a high frequency oscillator. The actualtuning element is a varactor diode, a 2-terminal device thatchanges capacitance as a function of reverse bias voltage.1 The oscillator is part of a frequency synthesizingloop, as detailed in Figure 1. A phase locked loop (PLL)compares a divided down representation of the oscillatorwith a frequency reference. The PLL’s output is levelshifted to provide the high voltage necessary to bias thevaractor, which closes a feedback loop by voltage tuningthe oscillator. This loop forces the voltage controlledoscillator (VCO) to operate at a frequency determined bythe frequency reference and the divider’s division ratio.
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented.
The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based phase-locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940).
The design is fully pipelined for maximum throughput.
