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The SL74HC573 is identical in pinout to the LS/ALS573. The device inputs are compatible with standard CMOS outputs with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
標(biāo)簽： compatible The 573 identical
上傳時(shí)間： 2016-12-29
上傳用戶：變形金剛
Datashet M28W320FST pinout .
標(biāo)簽： Datashet pinout W320 28W
上傳時(shí)間： 2017-03-01
上傳用戶：lijianyu172
pinout: STI5516 STI5517 Jtag pinout
標(biāo)簽： STI pinout pinout 5516
上傳時(shí)間： 2014-08-27
上傳用戶：小寶愛考拉
DELL AXIM x50v x51v pinout接口定義
標(biāo)簽： pinout DELL AXIM x50v
上傳時(shí)間： 2014-01-18
上傳用戶：chenbhdt
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, Òpinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
標(biāo)簽： MPC 106 PCI 存儲(chǔ)器
上傳時(shí)間： 2013-11-04
上傳用戶：as275944189
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上傳時(shí)間： 2013-11-10
上傳用戶：1427796291
The Hardware Book contains misc technical information about computers and other electronic devices. You ll find the pinout to most common (and uncommon) connectors availble, as well as info about how to build
標(biāo)簽： information electronic computers technical
上傳時(shí)間： 2013-12-13
上傳用戶：ommshaggar
An Arduino core for the ATmega328, ATmega168, ATmega88, ATmega48 and ATmega8, all running a [custom version of Optiboot for increased functionality](#write-to-own-flash). This core requires at least Arduino IDE v1.6.2, where v1.8.5+ is recommended. <br/> **This core gives you two extra IO pins if you're using the internal oscillator!** PB6 and PB7 is mapped to [Arduino pin 20 and 21](#pinout).<br/> If you're into "generic" AVR programming, I'm happy to tell you that all relevant keywords are being highlighted by the IDE through a separate keywords file. Make sure to test the [example files](https://github.com/MCUdude/MiniCore/tree/master/avr/libraries/AVR_examples/examples) (File > Examples > AVR C code examples). Try writing a register name, <i>DDRB</i> for instance, and see for yourself!
標(biāo)簽： MiniCore
上傳時(shí)間： 2021-02-22
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標(biāo)簽： DDR4
上傳時(shí)間： 2022-01-09
上傳用戶：
M.2的接口引腳定義，設(shè)計(jì)電路板的時(shí)候應(yīng)該用的著
標(biāo)簽： pcie
上傳時(shí)間： 2022-01-31
上傳用戶：jason_vip1
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