The core thrust of architecture has been to define core business requirements, and then construct the IT solution to meet those requirements, typically as instances of software. While this seems like a simple concept, many in enter- prise IT went way off course in the last 10 to 15 years.
標簽： Architecture Revolution Agile
上傳時間： 2020-05-26
上傳用戶：shancjb
This research work aims at eliminating the off-chip RF SAW filters from fre- quency division duplexed (FDD) receivers. In the first approach, a monolithic passive RF filter was constructed using on-chip capacitors and bondwire inductors. The bond- wire characteristics were studied in details and the effect of mutual inductive coupling between the bondwires on the filter performance was analyzed. Based on that, a bond- wire configuration was proposed to improve the frequency response of the filter. The filter was implemented in 0.18 μm CMOS process for WCDMA applications.
標簽： Interference Mitigation Techniques
上傳時間： 2020-05-27
上傳用戶：shancjb
his research aims at creating broadband tunable, fully integrated filters for the application of cognitive radio and signal classification receivers. The approach under study is the N-path filter technique which is capable of translating a baseband impedance to a reference frequency creating a tunable filter. The traditional N-path filter suffers from fundamental architectural limitations, namely : a trade-off between insertion loss and out-of-band rejection, reference clock feed- through, and jammer power handling limitations. In the first approach, the fundamental trade- off of the traditional N-path filter between insertion loss and out-of-band rejection is improved by a transmission line (T-line) N-path filter technique.
上傳時間： 2020-05-31
上傳用戶：shancjb
As we enter the next millennium, there are clear technological patterns. First, the electronic industry continues to scale microelectronic structures to achieve faster devices, new devices, or more per unit area. Secondly, electrostatic charge, electrostatic discharge (ESD), electrical overstress (EOS) and electromagnetic emissions (EMI) continue to be a threat to these scaled structures. This dichotomy presents a dilemma for the scaling of semiconductor technologies and a future threat to new technologies. Technological advancements, material changes, design techniques, and simulation can fend off this growing concern – but to maintain this ever-threatening challenge, one must continue to establish research and education in this issue.
標簽： ESD-Phenomena-and-the-Reliability
上傳時間： 2020-06-05
上傳用戶：shancjb
The continuous progress in modern power device technology is increasingly supported by power-specific modeling methodologies and dedicated simulation tools. These enable the detailed analysis of operational principles on the the device and on the system level; in particular, they allow the designer to perform trade- off studies by investigating the operation of competing design variants in a very early stage of the development process. Furthermore, using predictive computer simulation makes it possible to analyze the device and system behavior not only under regularoperatingconditions, but also at the rim of the safe-operatingarea and beyond of it, where destructive processes occur that limit the lifetime of a power system.
標簽： POWERHVMOS_Devices_Compact_Modeli ng
上傳時間： 2020-06-07
上傳用戶：shancjb
This book is about global navigation satellite systems (GNSS), their two main instru- ments, which are a receiver and a simulator, and their applications. The book is based on an operational off-the-shelf real-time software GNSS receiver and off-the-shelf GNSS signalsimulator.Theacademicversionsofthesetoolsarebundledwiththisbookandfree for readers to use for study and research.
標簽： Navigation Geophysics Satellite Digital and
上傳時間： 2020-06-09
上傳用戶：shancjb
General paradigm in solving a computer vision problem is to represent a raw image using a more informative vector called feature vector and train a classifier on top of feature vectors collected from training set. From classification perspective, there are several off-the-shelf methods such as gradient boosting, random forest and support vector machines that are able to accurately model nonlinear decision boundaries. Hence, solving a computer vision problem mainly depends on the feature extraction algorithm
標簽： Convolutional Networks Neural Guide to
上傳時間： 2020-06-10
上傳用戶：shancjb
USB_MICRO USB_MNI USB扁口座 TF卡槽 SOIC8 LQFP32芯片ALTIUM 庫（3D PCB封裝庫）, 3D封裝，已在項目中使用，可以做為你的設計參考。詳細列表如下：Component Count : 94Component Name-----------------------------------------------32165032-8MHZAMS1117ANT2AntennaBATbuzzerCapCAP-0805CAP-3216CD32Crystal Oscillator 3225HC-06KEY-2PINLED-0603LQFP-100LQFP32LQFP44LQFP44 10X10_LLQFP44 10X10_MLQFP44 10X10_NLQFP48LQFP48 7X7_LLQFP48 7X7_MLQFP48 7X7_NLQFP64 10x10_LLQFP64 10x10_MLQFP64 10x10_NMagMOTONRF24L01NRF24L01-modeOLED-0.96-PIN7QFN20_4X4QFN24_4X4QFN32_5X5remoteRES-0603RFX2401CRPSG90SH1.0mm-4PINSH1.0MM-5PINSH1.0mm-6PINSMA-ANTSMA/DO-214SOIC-8SOP16SOT-23-3SOT-23-5SOT-89SOT-223SPL06-001STM32F030C8T6STM32F030F4P6STM32F103C8T6straight-1x2pinstraight-1x2pin - duplicatestraight-1x2pin - duplicate1straight-1x3pinstraight-1x3pin - duplicatestraight-1x3pin - duplicate1straight-1x4pinstraight-1x4pin - duplicatestraight-1x5pinstraight-1x8pinstraight-1x8pin - duplicatestraight-2x2pinstraight-2x3pinstraight-2x4pinstraight-2x5pinSW-NO/OFF-PIN3SW-SMD1SW-SMD2SWITCH-DIP-6*6*7SX1308TF-CARDTO-263-5TP4056USBUSB_MICROUSB_MNI_BUSB-MICRO-1winding_1x2pinwinding_1x3pinwinding_1x4pinwinding_1x5pinwinding_1x8pinwinding_2x2pinwinding_2x3pinwinding_2x4pinwinding_2x5pinXTAL-5070/SMDXTAL-QC49/SMD
標簽： usb
上傳時間： 2021-12-02
上傳用戶：aben
采用的PLC是西門子S7-200系列，仿真編程軟件為STEP7-Micro。在初始狀態，容器是空的，各閥門皆關閉，Y1、Y2、Y3燈皆暗和M攪拌機均為OFF，液面傳感器L1、L2、L3為關，加熱器H為關。若要啟動操作，按下啟動按鈕(I0.0)，開始下列操作： （1）Y1、Y2為ON，液體A和B同時注入容器，當液面達到L2時，L2為ON，使Y1、Y2為OFF，Y3為ON，即關閉Y1、Y2閥門，打開液體C的閥門Y3。 （2）液面達到L1時，Y3為OFF，M為ON，即關閉閥門Y3，電動機起動開始攪拌。 （3）經10S攪勻后，M為OFF，停止攪拌，H為ON，加熱器開始加熱。 4、當混合液體溫度達到某一指定值時，T為ON，H為OFF，停止加熱，使電磁閥Y4為ON，開始放出混合液體。 （4）當液體高度降為L3后，L3從ON到OFF，再經5S，容器放空，Y4為OFF，開始下一周期。當按下停止按鈕后，在當前的混合操作處理完畢后，停止操作，停在初始狀態。
上傳時間： 2021-12-31
上傳用戶：XuVshu
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
