ReBEL is a Matlabtoolkit of functions and scripts, designed to
facilitate sequential Bayesian inference (estimation) in general state
space models. This software consolidates research on new methods for
recursive Bayesian estimation and Kalman filtering by Rudolph van der
Merwe and Eric A. Wan. The code is developed and maintained by Rudolph
van der Merwe at the OGI School of Science & Engineering at OHSU
(Oregon Health & Science University).
Knowledge of the process noise covariance matrix
is essential for the application of Kalman filtering. However,
it is usually a difficult task to obtain an explicit expression of
for large time varying systems. This paper looks at an adaptive
Kalman filter method for dynamic harmonic state estimation and
harmonic injection tracking.
This paper deals with the problem of speech enhancement when a
corrupted speech signal with an additive colored noise is the only
information available for processing. Kalman filtering is known as
an effective speech enhancement technique, in which speech signal
is usually modeled as autoregressive (AR) process and represented
in the state-space domain.
This paper deals with the problem of speech enhancement when
only a corrupted speech signal is available for processing. Kalman
filtering is known as an effective speech enhancement technique,
in which speech signal is usually modeled as autoregressive (AR)
model and represented in the state-space domain.
Demostration of example 6.2: Constrained Receding Horizon Control
Example retired from the book: Receding Horizon Control - Model Predictive Control for State Models
published on 2007-03-28
* "Copyright (c) 2006 Robert B. Reese ("AUTHOR")"
* All rights reserved.
* (R. Reese, reese@ece.msstate.edu, Mississippi State University)
* IN NO EVENT SHALL THE "AUTHOR" BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHOR"
* HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Verilog and VHDL狀態(tài)機設(shè)計，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding
presented. Different methodologies will be compared using real-world examples.
藍牙跳頻系統(tǒng)的simulink仿真程序（This is a MATLAB simulation (SIMULINK) for the hop selection scheme in Bluetooth. Since nearly the same scheme is used for 79 and 23-hop system. Only the 79-hop system in simulated in the CONNECTION state.）
this a pack include source code for quartus 2.
It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
