《單片機(jī)與嵌入式系統(tǒng)應(yīng)用》論文--嵌入式GSM短信息接口的軟硬件設(shè)計(jì)，文章給出一個(gè)小型的嵌入式SMS中/英文短信信息接口的設(shè)計(jì)，并詳細(xì)討論P(yáng)DU模式的短信息格式和中文短信息軟件解碼的設(shè)計(jì)。
上傳時(shí)間： 2013-07-12
上傳用戶：lanwei
·詳細(xì)說(shuō)明：雙音多頻（DTMF）信號(hào)發(fā)生器的使用源程序，vc 編寫(xiě)，與《雙音多頻（DTMF）接收器的使用源程序》聯(lián)合用- The double sound multi- frequencies (DTMF) the signal generating device use source program, the vc compilation, (DTMF) Receiver Use Source p
標(biāo)簽： DTMF 雙音多頻 信號(hào)發(fā)生器 源程序
上傳時(shí)間： 2013-07-23
上傳用戶：tianjinfan
SIM900A采用工業(yè)標(biāo)準(zhǔn)接口，工作頻率為GSM/GPRS 850/900/1800/1900MHz，可以低功耗實(shí)現(xiàn)語(yǔ)音、SMS、數(shù)據(jù)和傳真信息的傳輸。
上傳時(shí)間： 2013-05-19
上傳用戶：龍飛艇
Abstract: The MAX3108 is a complete high-performance universal asynchronous receiver-transmitter (UART) in a tiny 2.1mm ×
標(biāo)簽： Programming Rates Baud 3108
上傳時(shí)間： 2014-12-23
上傳用戶：清風(fēng)冷雨
The LT®6552 is a specialized dual-differencing 75MHzoperational amplifier ideal for rejecting common modenoise as a video line receiver. The input pairs are designedto operate with equal but opposite large-signal differencesand provide exceptional high frequency commonmode rejection (CMRR of 65dB at 10MHz), therebyforming an extremely versatile gain block structure thatminimizes component count in most situations. The dualinput pairs are free to take on independent common modelevels, while the two voltage differentials are summedinternally to form a net input signal.
上傳時(shí)間： 2014-12-23
上傳用戶：13691535575
Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.
標(biāo)簽： 數(shù)字接收器 信號(hào)鏈 噪聲分析
上傳時(shí)間： 2014-12-05
上傳用戶：cylnpy
Avalanche photo diode (APD) receiver modules arewidely used in fi ber optic communication systems. AnAPD module contains the APD and a signal conditioningamplifi er, but is not completely self contained. It stillrequires signifi cant support circuitry including a highvoltage, low noise power supply and a precision currentmonitor to indicate the signal strength. The challenge issqueezing this support circuitry into applications withlimited board space. The LT®3482 addresses this challengeby integrating a monolithic DC/DC step-up converter andan accurate current monitor. The LT3482 can supportup to a 90V APD bias voltage, and the current monitorprovides better than 10% accuracy over four decades ofdynamic range (250nA to 2.5mA).
上傳時(shí)間： 2014-01-18
上傳用戶：wenyuoo
介紹一種基于C8051F060單片機(jī)和NAND Flash的數(shù)據(jù)采集存儲(chǔ)系統(tǒng)，該系統(tǒng)可實(shí)現(xiàn)3路信號(hào)采樣，每路采樣率為5KS/s,通過(guò)異步串行通信接口實(shí)現(xiàn)數(shù)據(jù)傳輸。并詳細(xì)說(shuō)明系統(tǒng)的軟件設(shè)計(jì)。 Abstract: An acquisition and storage system based on C8051F060and NAND Flash is designed in this paper.The system is used to sample three-channel of signal,5KSPS each channel,and can upload data to test bench through UART（Universal Asynchronous Receiver/Transmitter）.The software design is discussed in detail.
標(biāo)簽： C8051F060 數(shù)據(jù)采集 存儲(chǔ)系統(tǒng)
上傳時(shí)間： 2013-10-12
上傳用戶：Jesse_嘉偉
在嵌入式系統(tǒng)中，嵌入式CPU往往要通過(guò)各種串行數(shù)據(jù)總線與“外界”進(jìn)行通信。在應(yīng)用中，異步的串行數(shù)據(jù)通信用得較多，而通用異步收發(fā)器UART（Universal Asynchronous Receiver Transmitter）在其中扮演著重要角色：完成數(shù)據(jù)的串并轉(zhuǎn)換，即把并行數(shù)據(jù)按照通信波特率轉(zhuǎn)化為通信協(xié)議中規(guī)定的串行數(shù)據(jù)流，也可從串行數(shù)據(jù)流中取出有用數(shù)據(jù)轉(zhuǎn)變?yōu)椴⑿袛?shù)據(jù)。而UART與CPU接口簡(jiǎn)單，CPU只需通過(guò)執(zhí)行讀寫(xiě)操作即可完成收發(fā)數(shù)據(jù)，從而完成與外界的通信。有許多現(xiàn)成的芯片可以實(shí)現(xiàn)UART的功能，如常用的Intel8250/8251接口芯片就可以作為RS232、RS422串口的UART控制芯片。
上傳時(shí)間： 2013-11-25
上傳用戶：www240697738
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
上傳時(shí)間： 2013-10-13
上傳用戶：ytulpx
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
