PXA270 design guide low level primitives
標(biāo)簽： primitives design guide level
上傳時(shí)間： 2014-06-30
上傳用戶：yxgi5
Firstly, this book is set at a level suitable for senior undergraduate and postgraduate students who wish to understand the fundamentals and applications of adaptive array antenna systems. Array fundamentals are described in the text, and examples which demonstrate theoretical concepts are included throughout the book, as well as summaries and questions at the end of each chapter.
標(biāo)簽： Applications Fundamentals Adaptive Systems Array and
上傳時(shí)間： 2020-05-26
上傳用戶：shancjb
This is the second edition of a textbook that is intended for a senior or graduate-level course in an electrical engineering (EE) curriculum on the subject of the analysis of multiconductor transmission lines (MTLs). It will also serve as a useful reference for industry professionals.
標(biāo)簽： Multiconductor Transmission Analysis Lines of
上傳時(shí)間： 2020-05-26
上傳用戶：shancjb
Three-Level Buck CFLY Balance and Control Methodology.
標(biāo)簽： CFLY
上傳時(shí)間： 2022-01-16
上傳用戶：
RISC-V 指令集手冊(cè) 卷 1：用戶級(jí)指令集體系結(jié)構(gòu)（User-Level ISA）
標(biāo)簽： RISC-V 指令集
上傳時(shí)間： 2022-06-18
上傳用戶：XuVshu
JPEG2000是由ISO/ITU-T組織下的IEC JTC1/SC29/WG1小組制定的下一代靜止圖像壓縮標(biāo)準(zhǔn).與JPEG(Joint Photographic Experts Group)相比,JPEG2000能夠提供更好的數(shù)據(jù)壓縮比,并且提供了一些JPEG所不具有的功能[1].JPEG2000具有的多種特性使得它具有廣泛的應(yīng)用前景.但是,JPEG2000是一個(gè)復(fù)雜編碼系統(tǒng),目前為止的軟件實(shí)現(xiàn)方案的執(zhí)行時(shí)間和所需的存儲(chǔ)量較大,若想將JPEG2000應(yīng)用于實(shí)際中,有著較大的困難,而用硬件電路實(shí)現(xiàn)JPEG2000或者其中的某些模塊,必然能夠減少JPEG200的執(zhí)行時(shí)間,因而具有重要的意義.本文首先簡(jiǎn)單介紹了JPEG2000這一新的靜止圖像壓縮標(biāo)準(zhǔn),然后對(duì)算術(shù)編碼的原理及實(shí)現(xiàn)算法進(jìn)行了深入的研究,并重點(diǎn)探討了JPEG2000中算術(shù)編碼的硬件實(shí)現(xiàn)問題,給出了一種硬件最優(yōu)化的算術(shù)編碼實(shí)現(xiàn)方案.最后使用硬件描述語(yǔ)言(Very High Speed Integrated Circuit Hardware Description Language,VHDL)在寄存器傳輸級(jí)(Register Transfer Level,RTL描述了該硬件最優(yōu)化的算術(shù)編碼實(shí)現(xiàn)方案,并以Altera 20K200E FPGA為基礎(chǔ),在Active-HDL環(huán)境中進(jìn)行了功能仿真,在Quartus Ⅱ集成開發(fā)環(huán)境下完成了綜合以及后仿真,綜合得到的最高工作時(shí)鐘頻率達(dá)45.81MHz.在相同的輸入條件下,輸出結(jié)果表明,本文設(shè)計(jì)的硬件算術(shù)編碼器與實(shí)現(xiàn)JPEG2000的軟件:Jasper[2]中的算術(shù)編碼模塊相比,處理時(shí)間縮短了30﹪左右.因而本文的研究對(duì)于JPEG2000應(yīng)用于數(shù)字監(jiān)控系統(tǒng)等實(shí)際應(yīng)用有著重要的意義.
標(biāo)簽： JPEG 2000 FPGA 算術(shù)編碼
上傳時(shí)間： 2013-05-16
上傳用戶：671145514
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時(shí)間： 2013-11-22
上傳用戶：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2014-12-23
上傳用戶：xinhaoshan2016
Methods for designing a maintenance simulation training system for certain kind of radio are introduced. Fault modeling method is used to establish the fault database. The system sets up some typical failures， follow the prompts trainers can locate the fault source and confirm the type to accomplish corresponding fault maintenance training. A training evaluation means is given to examining and evaluating the training performance. The system intuitively and vividly shows the fault maintenance process， it can not only be used in teaching， but also in daily maintenance training to efficiently improve the maintenance operation level. Graphical programming language LabVIEW is used to develop the system platform.
標(biāo)簽： 電臺(tái)維修 模擬訓(xùn)練 方法研究 系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-11-19
上傳用戶：3294322651
為了滿足現(xiàn)代高速通信中頻率快速轉(zhuǎn)換的需求，基于坐標(biāo)旋轉(zhuǎn)數(shù)字計(jì)算（CORDIC，Coordinate Rotation Digital Computer）算法完成正交直接數(shù)字頻率合成（ODDFS，Orthogonal Direct Digital Frequency Synthesizer）電路設(shè)計(jì)方案。采用MATLAB和Xilinx System Generator開發(fā)工具搭建電路的系統(tǒng)模型，通過現(xiàn)場(chǎng)可編程門陣列（FPGA，F(xiàn)ield Programmable Gate Array）完成電路的寄存器傳輸級(jí)（RTL，Register Transfer Level）驗(yàn)證，仿真結(jié)果表明電路設(shè)計(jì)具有很高的有效性和可行性。
標(biāo)簽： CORDIC ODDFS 算法 電路設(shè)計(jì)
上傳時(shí)間： 2013-11-09
上傳用戶：hfnishi
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
