flash serial input queue. returns 0 on success or negative error * number otherwise
標(biāo)簽： otherwise negative returns success
上傳時(shí)間： 2015-11-13
上傳用戶：yxgi5
Filo serial-Input to Paralle-output
標(biāo)簽： Paralle-output serial-Input Filo to
上傳時(shí)間： 2014-01-16
上傳用戶：evil
英文描述： 8-Bit serial-Input/Parallel-Output Shift Register 中文描述： 8位serial-Input/Parallel-Output移位寄存器
上傳時(shí)間： 2013-04-24
上傳用戶：epson850
-- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous -- LOAD active : high -- CE active : high -- SERIAL input : SI
標(biāo)簽： Shift right DESCRIPTION direction
上傳時(shí)間： 2013-12-02
上傳用戶：gxrui1991
Single-Channel, Serial Input, 4 mA to20 mA, Current Source DAC, HART Connectivity
上傳時(shí)間： 2022-07-24
上傳用戶：
RS232.C was written to provide all of the basic functionality needed to employ serial I/O in any application written with Borland C language compilers. Some features are: 1. Ease of use. No assembly language or library files are used and a simple "#include" statement is all that is required to access all of the functions provided. 2. Both input and output are buffered and interrupt driven for efficiency. 3. Serial ports 1 - 4 are supported on PC, AT and PS/2 compatibles.Chained interrupts used on port 3 and 4 are allowed for so as not to interfere with devices such as a mouse or printer. Transmission speeds of 110 to 115200 baud are available. 4. Detection and utilization of hardware buffered UARTs (NS16550AF etc.) found in some machines is automatic. 5. Interrupt driven hardware and XON/XOFF flow control is provided for. 6. All source code is included. RS232.C can be used with all memory models.
標(biāo)簽： functionality provide written employ
上傳時(shí)間： 2016-08-24
上傳用戶：小眼睛LSL
實(shí)現(xiàn)實(shí)時(shí)語音的錄入以及與RS232串口完美結(jié)合-Real-time voice input and the perfect combination with the RS232 serial port
上傳時(shí)間： 2013-05-16
上傳用戶：大三三
fpga/CPLD開發(fā)管理Digit-Serial DSP Functions
標(biāo)簽： Digit-Serial Functions fpga CPLD
上傳時(shí)間： 2013-08-30
上傳用戶：lz4v4
Abstract: This document details the Lakewood (MAXREFDES7#) subsystem reference design, a 3.3V input, ±12V (±15V) output, isolated power supply. The Lakewood reference design includes a 3W primary-side transformer H-bridge driver for isolated supplies, and two wide input range and adjustable output low-dropout linear regulators (LDOs). Test results and hardware files are included.
標(biāo)簽： MAXREFDES Lakewood Isolated Output
上傳時(shí)間： 2013-11-02
上傳用戶：fengzimili
Abstract: This document details the Riverside (MAXREFDES8#) subsystem reference design, a 3.3V input, 12V (15V) output, isolated power supply. The Riverside reference design includes a 3W primary-side transformer H-bridge driver for isolated supplies, and one wide input range and adjustable output low-dropout linear regulator (LDO). Test results and hardware files are included.
標(biāo)簽： Riverside MAXREFDES Isolated Output
上傳時(shí)間： 2013-11-16
上傳用戶：會(huì)稽劍客
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