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使用Nios II緊耦合存儲(chǔ)器教程

使用Nios II緊耦合存儲(chǔ)器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5

標(biāo)簽： Nios 耦合存儲(chǔ)器教程

上傳時(shí)間： 2013-10-13

上傳用戶：黃婷婷思密達(dá)
Nios II軟件開發(fā)人員手冊中的緩存和緊耦合存儲(chǔ)器部分

Nios II 軟件開發(fā)人員手冊中的緩存和緊耦合存儲(chǔ)器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:

標(biāo)簽： Nios 軟件開發(fā) 存儲(chǔ)器

上傳時(shí)間： 2013-10-25

上傳用戶：蟲蟲蟲蟲蟲蟲
Nios II定制指令用戶指南

Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.

標(biāo)簽： Nios 定制指令用戶

上傳時(shí)間： 2013-10-12

上傳用戶：kang1923
Nios II 系列處理器配置選項(xiàng)

Nios II 系列處理器配置選項(xiàng):This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.

標(biāo)簽： Nios II 列處理器

上傳時(shí)間： 2015-01-01

上傳用戶：mahone
Nios II內(nèi)核詳細(xì)實(shí)現(xiàn)

Nios II內(nèi)核詳細(xì)實(shí)現(xiàn)

標(biāo)簽： Nios 內(nèi)核

上傳時(shí)間： 2015-01-01

上傳用戶：源碼3
XAPP380 -利用CoolRunner-II CPLD創(chuàng)建交叉點(diǎn)開關(guān)

This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.

標(biāo)簽： CoolRunner-II XAPP CPLD 380

上傳時(shí)間： 2013-10-26

上傳用戶：kiklkook
XAPP944 - 將Xilinx CoolRunner-II CPLD用作數(shù)據(jù)流開關(guān)

This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources

標(biāo)簽： CoolRunner-II Xilinx XAPP CPLD

上傳時(shí)間： 2013-12-16

上傳用戶：qwer0574
東南大學(xué)綜合電子實(shí)踐Quartus ii課程設(shè)計(jì)報(bào)告

東南大學(xué)綜合電子實(shí)踐Quartus ii課程設(shè)計(jì)報(bào)告包含跑馬燈，數(shù)字鐘和交通燈設(shè)計(jì)

標(biāo)簽： Quartus 東南大學(xué) 電子實(shí)踐

上傳時(shí)間： 2015-01-02

上傳用戶：超凡大師
XAPP904 - CoolRunner-II特性LCD模塊接口

There are many manufacturers of dot matrix LCD modules. However, most of these displaysare similar. They all have on-board controllers and drivers capable of displaying alpha numericsand a wide variety of other symbols (including Japanese "Katakana" characters). The internaloperation of LCD controller devices is determined by signals sent from a central processing unit(in this case, a CoolRunner-II CPLD).

標(biāo)簽： CoolRunner-II XAPP 904 LCD

上傳時(shí)間： 2013-12-17

上傳用戶：haiya2000
SECS I, SECS II協(xié)議通訊源碼

SECS I, SECS II協(xié)議通訊源碼

標(biāo)簽： SECS 協(xié)議通訊源碼

上傳時(shí)間： 2015-01-04

上傳用戶：qq1604324866

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