·Verilog HDL synThesis, A Practical Primer
標(biāo)簽： nbsp synThesis Practical Verilog
上傳時(shí)間： 2013-04-24
上傳用戶：muhongqing
·Advanced ASIC Chip synThesis Using Synopsys Design Compiler,Physical Compiler and Primetime
標(biāo)簽： nbsp synThesis Advanced Synopsys
上傳時(shí)間： 2013-04-24
上傳用戶：alia
直接數(shù)字頻率合成（Direct Digital Fraquency synThesis,即DDFS，一般簡稱DDS）是從相位概念出發(fā)直接合成所需要波形的一種新的頻率合成技術(shù)。
標(biāo)簽： Fraquency synThesis Digital Direct
上傳時(shí)間： 2013-08-27
上傳用戶：wpt
FPGA synThesis with the Synplify Pro Tool
標(biāo)簽： synThesis Synplify FPGA with
上傳時(shí)間： 2013-09-04
上傳用戶：sevenbestfei
本文論述了狀態(tài)機(jī)的verilog編碼風(fēng)格,以及不同編碼風(fēng)格的優(yōu)缺點(diǎn)，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for synThesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
標(biāo)簽： synThesis Machine Coding Styles
上傳時(shí)間： 2013-10-15
上傳用戶：dancnc
本文論述了狀態(tài)機(jī)的verilog編碼風(fēng)格,以及不同編碼風(fēng)格的優(yōu)缺點(diǎn)，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for synThesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
標(biāo)簽： synThesis Machine Coding Styles
上傳時(shí)間： 2013-10-12
上傳用戶：sardinescn
State.Machine.Coding.Styles.for.synThesis（狀態(tài)機(jī)，英文,VHDL）
標(biāo)簽： synThesis Machine Coding Styles
上傳時(shí)間： 2013-12-22
上傳用戶：vodssv
Simulation and synThesis Techniques for Asynchronous FIFO Design
標(biāo)簽： Asynchronous Simulation Techniques synThesis
上傳時(shí)間： 2013-12-10
上傳用戶：songnanhua
FPGA synThesis with the Synplify Pro Tool
標(biāo)簽： synThesis Synplify FPGA with
上傳時(shí)間： 2015-04-25
上傳用戶：guanliya
Xilinx synThesis & Simulation Design Guide
標(biāo)簽： Simulation synThesis Xilinx Design
上傳時(shí)間： 2013-12-26
上傳用戶：xsnjzljj
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