Industrial systems demand semiconductors that are precise, flexibleand reliable. Linear Technology offers a broad line of high performanceanalog ICs that simplify system design with rugged devices featuringparameters fully guaranteed over the -40°C to 85°C temperature range.We back this up with knowledgeable applications support, long productlife cycles and superior on-time delivery.
上傳時間： 2013-11-02
上傳用戶：xiaodu1124
Xilinx公司推出的DSP設計開發工具System Generator是在Matlab環境中進行建模，是DSP高層系統設計與Xilinx FPGA之間實現的“橋梁”。在分析了FPGA傳統級設計方法的基礎上，提出了基于System Generator的系統級設計新方法，并應用新方法設計驗證了一套數字下變頻系統，通過仿真和實驗結果驗證了該方法的有效性和準確性。
上傳時間： 2013-11-18
上傳用戶：小草123
Abstract: Using a DAC and a microprocessor supervisor, the system safety can be improved in industrial controllers, programmablelogiccontrollers (PLC), and data-acquisition systems. The analog output is set to zero-scale (or pin-programmable midscale) when amicroprocessor failure, optocoupler failure, or undervoltage condition occurs. A simple application is shown on how to implement thisfunction.
上傳時間： 2013-10-17
上傳用戶：sjb555
Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.
上傳時間： 2014-12-05
上傳用戶：cylnpy
A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz clock speed.
上傳時間： 2013-10-29
上傳用戶：BOBOniu
•Founded in Jan. 08, 2001 in Shanghai, China.•Fabless IDH focused on Analog & Mixed Signal Chip design & marketing •Over 100 IC introduced.•Over 200 OEM Customer worldwide•ISO-9000 Certified•Distribution Channel in Taiwan, China & Japan To achieve 100% customer satisfactionby producing the technically advanced product with the best quality, on-time delivery and service. Leverages on proprietary process and world-class engineering team to develop innovative & high quality analog solutions that add value to electronics equipment.
標簽： Circuit Analog Design Porta
上傳時間： 2013-10-24
上傳用戶：songnanhua
高速數字系統設計下載pdf:High-Speed Digital SystemDesign—A Handbook ofInterconnect Theory and DesignPracticesStephen H. HallGarrett W. HallJames A. McCallA Wiley-Interscience Publication JOHN WILEY & SONS, INC.New York • Chichester • Weinheim • Brisbane • Singapore • TorontoCopyright © 2000 by John Wiley & Sons, Inc.speeddigital systems at the platform level. The book walks the reader through everyrequired concept, from basic transmission line theory to digital timing analysis, high-speedmeasurement techniques, as well as many other topics. In doing so, a unique balancebetween theory and practical applications is achieved that will allow the reader not only tounderstand the nature of the problem, but also provide practical guidance to the solution.The level of theoretical understanding is such that the reader will be equipped to see beyondthe immediate practical application and solve problems not contained within these pages.Much of the information in this book has not been needed in past digital designs but isabsolutely necessary today. Most of the information covered here is not covered in standardcollege curricula, at least not in its focus on digital design, which is arguably one of the mostsignificant industries in electrical engineering.The focus of this book is on the design of robust high-volume, high-speed digital productssuch as computer systems, with particular attention paid to computer busses. However, thetheory presented is applicable to any high-speed digital system. All of the techniquescovered in this book have been applied in industry to actual digital products that have beensuccessfully produced and sold in high volume.Practicing engineers and graduate and undergraduate students who have completed basicelectromagnetic or microwave design classes are equipped to fully comprehend the theorypresented in this book. At a practical level, however, basic circuit theory is all thebackground required to apply the formulas in this book.
上傳時間： 2013-10-26
上傳用戶：縹緲
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
電子設備的 ON/OFF 按鈕給繫統設計師帶來了一組獨特的挑戰
上傳時間： 2013-10-13
上傳用戶：18165383642
Multiple-voltage electronics systems often requirecomplex supply voltage tracking or sequencing, whichif not met, can result in system faults or even permanentfailures in the fi eld. The design diffi culties in meetingthese requirements are often compounded in distributedpowerarchitectures where point-of-load (POL) DC/DCconverters or linear regulators are scattered across PCboard space, sometimes on different board planes. Theproblem is that power supply circuitry is often the lastcircuitry to be designed into the board, and it must beshoehorned into whatever little board real estate is left.Often, a simple, drop-in, fl exible solution is needed tomeet these requirements.
上傳時間： 2013-10-08
上傳用戶：15071087253
