This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
標簽： Development Startix2 tailored Altera
上傳時間： 2014-01-19
上傳用戶：chongcongying
A Zilog Z80 simulator, debugger and profiler tailored for ZX Spectrum development (but generic enough to be used with other platforms)
標簽： development simulator Spectrum debugger
上傳時間： 2016-05-26
上傳用戶：love_stanford
This white paper raises some fundamental issues the design engineer should address before deciding upon a communication approach for a wireless network. As no universal wireless network solution exists, it should be custom tailored to suit the application demands. Defining your application communication characteristics is the key to ensure optimal communication reliability and resistance to interfering noise sources.
上傳時間： 2013-11-23
上傳用戶：zhichenglu
This program accesses a SPI EEPROM using polled mode access. The F12x MCU is configured in 4-wire Single Master Mode, and the EEPROM is the only slave device connected to the SPI bus. The read/write operations are tailored to access a Microchip 4 kB EEPROM
標簽： configured accesses program EEPROM
上傳時間： 2016-03-29
上傳用戶：gut1234567
// This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
標簽： configured accesses program EEPROM
上傳時間： 2014-01-18
上傳用戶：liglechongchong
// This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
標簽： configured accesses program EEPROM
上傳時間： 2016-04-12
上傳用戶：qb1993225
The MIPS32® 4KEm™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family. It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The 4KEm core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
標簽： MIPS 8482 Technologies 174
上傳時間： 2014-12-22
上傳用戶：semi1981
