In C Algorithms for Real-Time DSP, author Paul M. Embree presents a complete guide to digital signal processing techniques in the C programming language. This book is structured in such a way that it will be most useful to the engineer who is familiar with DSP and the C language, but who is not necessarily an expert in both. All of the example programs in this book have been tested using standard C compilers in the UNIX and MS-DOS programming environments. In addition, the examples have been compiled using the real-time programing tools of specific real-time embedded DSP microprocessors (Analog Devices ADSP-21020 and ADSP-21062 texas Instruments TMS320C30 and TMS320C40 and AT&T DSP32C) and then tested with real-time hardware using real-world signals.
標(biāo)簽： M. Algorithms Real-Time complete
上傳時(shí)間： 2014-01-07
上傳用戶：epson850
Commercially available active noise control headphones rely on fixed analog controllers to drive "anti-noise" loudspeakers. Our design uses an adaptive controller to optimally cancel unwanted acoustic noise. This headphone would be particularly useful for workers who operate or work near heavy machinery and engines because the noise is selectively eliminated. Desired sounds, such as speech and warning signals, are left to be heard clearly. The adaptive control algorithm is implemented on a texas Instruments (TI™ ) 1 TMS320C30GEL digital signal processor (DSP), which drives a Sony CD550 headphone/microphone system. Our experiments indicate that adaptive noise control results in a dramatic improvement in performance over fixed noise control. This improvement is due to the availability of high-performance programmable DSPs and the self-optimizing and tracking capabilities of the adaptive controller in response to the surrounding noise.
標(biāo)簽： Commercially controllers headphones available
上傳時(shí)間： 2013-12-04
上傳用戶：dyctj
DESCRIPTION The texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs. The MSP430G2x13 and MSP430G2x53 series are ultra-low-power mixed signal microcontrollers with built-in 16- bit timers, up to 24 I/O capacitive-touch enabled pins, a versatile analog comparator, and built-in communication capability using the universal serial communication interface. In addition the MSP430G2x53 family members have a 10-bit analog-to-digital (A/D) converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.
標(biāo)簽： G2553 2553 430G MSP 430
上傳時(shí)間： 2018-12-25
上傳用戶：ygyh
ccs6.1.2軟件的安裝使用方法，以及在simlulink庫中c2000處理器支持的embedded coder support package for texas instrument c2000 processors
標(biāo)簽： ccs6 1.2 軟件開發(fā)環(huán)境
上傳時(shí)間： 2019-07-20
上傳用戶：葉落風(fēng)行
texas instruments MIPI DSI to eDP converter. Input supports 2 channel, 4 lanes each, up to 1.5GBit/s. Total input bandwidth is 12Gbit/s. Output eDP 1.4 1,2 or 4 lanes up to 5.4Gbit/s. output up to 4096x2304 60fps.
上傳時(shí)間： 2021-12-22
上傳用戶：
ADS1256 是TI（texas I nstruments ）公司推出的一款低噪聲高分辨率的24 位Si gma - Delta（"- #）模數(shù)轉(zhuǎn)換器（ADC）。"- #ADC 與傳統(tǒng)的逐次逼近型和積分型ADC 相比有轉(zhuǎn)換誤差小而價(jià)格低廉的優(yōu)點(diǎn)，但由于受帶寬和有效采樣率的限制，"- #ADC 不適用于高頻數(shù)據(jù)采集的場合。該款A(yù)DS1256 可適合于采集最高頻率只有幾千赫茲的模擬數(shù)據(jù)的系統(tǒng)中，數(shù)據(jù)輸出速率最高可為30K 采樣點(diǎn)／秒（SPS），有完善的自校正和系統(tǒng)校正系統(tǒng)， SPI 串行數(shù)據(jù)傳輸接口。本文結(jié)合筆者自己的應(yīng)用經(jīng)驗(yàn)，對該ADC 的基本原理以及應(yīng)用做簡要介紹。ADs1256 的總體電氣特性下面介紹在使用ADs1256 的過程中要注意的一些電氣方面的具體參數(shù)：模擬電源（AVDD ）輸入范圍+ 4 . 75V !+ 5 .25V，使用的典型值為+ 5 .00V；數(shù)字電源（DVDD ）輸入范圍+ 1 . 8V !+ 3 .6V，使用的典型值+ 3 .3V；參考電壓值（VREF= VREFP- VREFN）的范圍+ 0 .5V!+ 2 .6V，使用的典型值為+ 2 .5V；耗散功率最大為57mW；每個(gè)模擬輸入端（AI N0 !7 和AI NC M）相對于模擬地（AGND）的絕對電壓值范圍在輸入緩沖器（BUFFER）關(guān)閉的時(shí)候?yàn)锳GND-0 .1 !AVDD+ 0 . 1 ，在輸入緩沖器打開的時(shí)候?yàn)锳GND !AVDD-2 .0 ；滿刻度差分模擬輸入電壓值（VI N = AI NP -AI NN）為+ ／-（2VREF／PGA）；數(shù)字輸入邏輯高電平范圍0 .8DVDD!5 .25V（除D0 !D3 的輸入點(diǎn)平不可超過DVDD 外），邏輯低點(diǎn)平范圍DGND!0 .2DVDD；數(shù)字輸出邏輯高電平下限為0 .8DVDD，邏輯低電平上限為0 .2DVDD，輸出電流典型值為5mA；主時(shí)鐘頻率由外部晶體振蕩器提供給XTAL1和XTAL2 時(shí)，要求范圍為2 M!10 MHz ，僅由CLKI N 輸入提供時(shí)，范圍為0 .1 M!10 MHz 。
上傳時(shí)間： 2022-06-10
上傳用戶：
IEEE1149.1的產(chǎn)生1985年由IBM、AT&T、texas Instruments、Philips Electronics NV、Siemens、Alcatel和Ericsson等公司成立的JETAG（Joint European Test Action Group）提出了邊界掃描技術(shù)。1986年由于其它地區(qū)的一些公司的加入，JETAG改名為JTAG。1988年JTAG提出了標(biāo)準(zhǔn)的邊界掃描體系結(jié)構(gòu)，名稱叫Boundary-Scan Architecture Standard Proposal，Version2.0，1990年IEEE正式承認(rèn)了JTAG標(biāo)準(zhǔn)，經(jīng)過補(bǔ)充和修訂以后命名命名為IEEE1149.1-90。同年又提出了BSDL（Boundary Scan Description Lauguage，邊界掃描描述語言）。后來成為IEEE1149.1-93標(biāo)準(zhǔn)的一部分。
標(biāo)簽： jtag
上傳時(shí)間： 2022-07-06
上傳用戶：canderile
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