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three-input

  • 電感開(kāi)關(guān)穩(wěn)壓器提高輸入電壓

    Abstract: Uses the MAX641 switching controller and an external discrete charge pump to step up the input voltage. This circuitcan service low loads and is efficient when the output is two, three, four times the input voltage. Adding the MAX627 MOSdriver can further increase the output current capability.

    標(biāo)簽: 電感 開(kāi)關(guān)穩(wěn)壓器 輸入電壓

    上傳時(shí)間: 2013-11-15

    上傳用戶:zwei41

  • Wide-input dc/dc modules offer

    When a system designer specifies a nonisolated dc/dc powermodule, considering the needed input voltage range isequally as important as considering the required performanceattributes and features. Generally, nonisolated moduleshave either a narrow or a wide input voltage range. Narrowinputmodules typically have a nominal input voltage of3.3, 5, or 12 V. For systems that operate from a tightlyregulated input bus—such as those that do not use batterybackup—a narrow-input module is often adequate sincethe input remains fairly stable.Offering greater flexibility, wide-input modules operatewithin a range of 7 to 36 V, which includes the popular12- or 24-V industrial bus. This enables a single module tobe used for generating multiple voltages. These modulesare ideal for industrial controls, HVAC systems, vehicles,medical instrumentation, and other applications that usea loosely regulated distribution bus. In addition, systemspowered by a rectifier/battery charger with lead-acidbattery backup almost always require wide-input modules.System designers who choose power supplies may wantto take a close look at the latest generation of wide-inputdc/dc modules.

    標(biāo)簽: Wide-input modules offer dc

    上傳時(shí)間: 2014-12-24

    上傳用戶:dragonhaixm

  • SN65LBC170,SN75LBC170,pdf(TRIP

    The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.

    標(biāo)簽: 170 LBC SN TRIP

    上傳時(shí)間: 2013-10-13

    上傳用戶:ytulpx

  • Input Signal Rise and Fall Tim

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.

    標(biāo)簽: Signal Input Fall Rise

    上傳時(shí)間: 2013-10-23

    上傳用戶:copu

  • Award BIOS(Basic Input/Output System)(電腦啟動(dòng)時(shí)所必需)的源碼

    Award BIOS(Basic Input/Output System)(電腦啟動(dòng)時(shí)所必需)的源碼

    標(biāo)簽: Output System Award Basic

    上傳時(shí)間: 2014-01-04

    上傳用戶:ecooo

  • PQP is a library for performing three types of proximity queries on a pair of geometric models compo

    PQP is a library for performing three types of proximity queries on a pair of geometric models composed of triangles:

    標(biāo)簽: performing geometric proximity library

    上傳時(shí)間: 2014-01-13

    上傳用戶:love_stanford

  • This program can determin very accurately the nature of the user input

    This program can determin very accurately the nature of the user input

    標(biāo)簽: accurately the determin program

    上傳時(shí)間: 2015-01-28

    上傳用戶:shinesyh

  • 生成BCD碼。 Name: BIN3toBCD4 Func:2字節(jié)二進(jìn)制整數(shù)--->>BCD碼四字節(jié)轉(zhuǎn)換(Comped BCD) Input: 3進(jìn)制數(shù)人低字節(jié)到高字節(jié)存放在內(nèi)部RAM50

    生成BCD碼。 Name: BIN3toBCD4 Func:2字節(jié)二進(jìn)制整數(shù)--->>BCD碼四字節(jié)轉(zhuǎn)換(Comped BCD) Input: 3進(jìn)制數(shù)人低字節(jié)到高字節(jié)存放在內(nèi)部RAM50H,51H,52h單元中 Output: BCD碼人低位到高位分別存放在內(nèi)部RAM53H,54H,55H,56H單元中 USE: R7-R0, 56H-50H

    標(biāo)簽: BCD BIN3toBCD4 Comped Input

    上傳時(shí)間: 2015-02-02

    上傳用戶:FreeSky

  • The VideoTransmit class is a simple wrapper that can be programmed to take video input from a source

    The VideoTransmit class is a simple wrapper that can be programmed to take video input from a source of your choice and transmit the video to a destination computer or network in JPEG format.

    標(biāo)簽: VideoTransmit programmed wrapper simple

    上傳時(shí)間: 2014-01-06

    上傳用戶:zhuyibin

  • The audioTransmit class is a simple wrapper that can be programmed to take audio input from a source

    The audioTransmit class is a simple wrapper that can be programmed to take audio input from a source of your choice and transmit the audio to a destination computer

    標(biāo)簽: audioTransmit programmed wrapper simple

    上傳時(shí)間: 2013-12-16

    上傳用戶:sjyy1001

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