Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
標(biāo)簽： Synthesis Advanced Synopsys Compiler
上傳時(shí)間： 2017-04-04
上傳用戶：lanwei
The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
標(biāo)簽： increasingly description designing languages
上傳時(shí)間： 2014-01-08
上傳用戶：小草123
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary ROM 512 bytes of on-chip RAM four 8-bit bi-directional and bit-addressable I/O ports an additional 4- bit port P4 three 16-bit timer/counters a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78E58B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security
標(biāo)簽： microcontroller programmable in-system W78E58B
上傳時(shí)間： 2017-04-27
上傳用戶：yiwen213
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
標(biāo)簽： application real-time Synopsys emphasis
上傳時(shí)間： 2017-07-05
上傳用戶：waitingfy
The idea for this book was born during one of my project-related trips to the beautiful city of Hangzhou in China, where in the role of Chief Architect I had to guide a team of very young, very smart and extremely dedicated software developers and verification engineers. Soon it became clear that as eager as the team was to jump into the coding, it did not have any experience in system architecture and design and if I did not want to spend all my time in constant travel between San Francisco and Hangzhou, the only option was to groom a number of local junior architects. Logically, one of the first questions being asked by these carefully selected future architects was whether I could recommend a book or other learning material that could speed up the learning cycle. I could not. Of course, there were many books on various related topics, but many of them were too old and most of the updated information was either somewhere on the Internet dispersed between many sites and online magazines, or buried in my brain along with many years of experience of system architecture.
標(biāo)簽： Telecommunication Gateways System Design for
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
上傳時(shí)間： 2021-11-09
上傳用戶：
ISO 26262《道路車輛功能安全》國際標(biāo)準(zhǔn)是針對總重不超過3.5噸八座乘用車，以安全相關(guān)電子電氣系統(tǒng)的特點(diǎn)所制定的功能安全標(biāo)準(zhǔn)，基于IEC 61508《安全相關(guān)電氣/電子/可編程電子系統(tǒng)功能安全》制定，在2011年11月15日正式發(fā)布。ISO 26262是史上第一個(gè)適用于大批量量產(chǎn)產(chǎn)品的功能安全（Functional Safety）標(biāo)準(zhǔn)。特別需要注意的是，ISO 26262僅針對安全相關(guān)電子電氣系統(tǒng)，包含電機(jī)、電子與軟件零件，不應(yīng)用于非電子電氣系統(tǒng)（如機(jī)械、液壓等）。功能安全之設(shè)計(jì)議題在汽車領(lǐng)域已被重視，因其關(guān)系人員安全與公司商譽(yù)等問題，透過危害分析與風(fēng)險(xiǎn)評估（Hazard Analysis & Risk Assessment，HARA）及V模型設(shè)計(jì)架構(gòu)，使功能安全需求等級得到一致性的分析結(jié)果，以利汽車電子系統(tǒng)之生命周期考慮到所需失效防止技術(shù)與管理要求，并借由設(shè)計(jì)開發(fā)、查證（verification）及確認(rèn)（Validation）等能力成熟度模型集成（CMMI-DEV）流程加以實(shí)現(xiàn)，使得產(chǎn)品之功能安全符合所需汽車安全完整性等級（ASIL）。
標(biāo)簽： 道路車輛功能安全 iso26262 國際標(biāo)準(zhǔn)
上傳時(shí)間： 2022-05-30
上傳用戶：
ISO 26262《道路車輛功能安全》國際標(biāo)準(zhǔn)是針對總重不超過3.5噸八座乘用車，以安全相關(guān)電子電氣系統(tǒng)的特點(diǎn)所制定的功能安全標(biāo)準(zhǔn)，基于IEC 61508《安全相關(guān)電氣/電子/可編程電子系統(tǒng)功能安全》制定，在2011年11月15日正式發(fā)布。ISO 26262是史上第一個(gè)適用于大批量量產(chǎn)產(chǎn)品的功能安全（Functional Safety）標(biāo)準(zhǔn)。特別需要注意的是，ISO 26262僅針對安全相關(guān)電子電氣系統(tǒng)，包含電機(jī)、電子與軟件零件，不應(yīng)用于非電子電氣系統(tǒng)（如機(jī)械、液壓等）。功能安全之設(shè)計(jì)議題在汽車領(lǐng)域已被重視，因其關(guān)系人員安全與公司商譽(yù)等問題，透過危害分析與風(fēng)險(xiǎn)評估（Hazard Analysis & Risk Assessment，HARA）及V模型設(shè)計(jì)架構(gòu)，使功能安全需求等級得到一致性的分析結(jié)果，以利汽車電子系統(tǒng)之生命周期考慮到所需失效防止技術(shù)與管理要求，并借由設(shè)計(jì)開發(fā)、查證（verification）及確認(rèn)（Validation）等能力成熟度模型集成（CMMI-DEV）流程加以實(shí)現(xiàn)，使得產(chǎn)品之功能安全符合所需汽車安全完整性等級（ASIL）。
標(biāo)簽： 道路車輛功能安全 iso26262 國際標(biāo)準(zhǔn)
上傳時(shí)間： 2022-05-30
上傳用戶：
ISO 26262《道路車輛功能安全》國際標(biāo)準(zhǔn)是針對總重不超過3.5噸八座乘用車，以安全相關(guān)電子電氣系統(tǒng)的特點(diǎn)所制定的功能安全標(biāo)準(zhǔn)，基于IEC 61508《安全相關(guān)電氣/電子/可編程電子系統(tǒng)功能安全》制定，在2011年11月15日正式發(fā)布。ISO 26262是史上第一個(gè)適用于大批量量產(chǎn)產(chǎn)品的功能安全（Functional Safety）標(biāo)準(zhǔn)。特別需要注意的是，ISO 26262僅針對安全相關(guān)電子電氣系統(tǒng)，包含電機(jī)、電子與軟件零件，不應(yīng)用于非電子電氣系統(tǒng)（如機(jī)械、液壓等）。功能安全之設(shè)計(jì)議題在汽車領(lǐng)域已被重視，因其關(guān)系人員安全與公司商譽(yù)等問題，透過危害分析與風(fēng)險(xiǎn)評估（Hazard Analysis & Risk Assessment，HARA）及V模型設(shè)計(jì)架構(gòu)，使功能安全需求等級得到一致性的分析結(jié)果，以利汽車電子系統(tǒng)之生命周期考慮到所需失效防止技術(shù)與管理要求，并借由設(shè)計(jì)開發(fā)、查證（verification）及確認(rèn)（Validation）等能力成熟度模型集成（CMMI-DEV）流程加以實(shí)現(xiàn)，使得產(chǎn)品之功能安全符合所需汽車安全完整性等級（ASIL）。
標(biāo)簽： 道路車輛功能安全 iso26262 國際標(biāo)準(zhǔn)
上傳時(shí)間： 2022-05-30
上傳用戶：得之我幸78
ISO 26262《道路車輛功能安全》國際標(biāo)準(zhǔn)是針對總重不超過3.5噸八座乘用車，以安全相關(guān)電子電氣系統(tǒng)的特點(diǎn)所制定的功能安全標(biāo)準(zhǔn)，基于IEC 61508《安全相關(guān)電氣/電子/可編程電子系統(tǒng)功能安全》制定，在2011年11月15日正式發(fā)布。ISO 26262是史上第一個(gè)適用于大批量量產(chǎn)產(chǎn)品的功能安全（Functional Safety）標(biāo)準(zhǔn)。特別需要注意的是，ISO 26262僅針對安全相關(guān)電子電氣系統(tǒng)，包含電機(jī)、電子與軟件零件，不應(yīng)用于非電子電氣系統(tǒng)（如機(jī)械、液壓等）。功能安全之設(shè)計(jì)議題在汽車領(lǐng)域已被重視，因其關(guān)系人員安全與公司商譽(yù)等問題，透過危害分析與風(fēng)險(xiǎn)評估（Hazard Analysis & Risk Assessment，HARA）及V模型設(shè)計(jì)架構(gòu)，使功能安全需求等級得到一致性的分析結(jié)果，以利汽車電子系統(tǒng)之生命周期考慮到所需失效防止技術(shù)與管理要求，并借由設(shè)計(jì)開發(fā)、查證（verification）及確認(rèn)（Validation）等能力成熟度模型集成（CMMI-DEV）流程加以實(shí)現(xiàn)，使得產(chǎn)品之功能安全符合所需汽車安全完整性等級（ASIL）。
標(biāo)簽： 道路車輛功能安全 iso26262 國際標(biāo)準(zhǔn)
上傳時(shí)間： 2022-05-30
上傳用戶：
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