Verilog code for RS-(255,239) encoder.
資源簡(jiǎn)介:Verilog code for RS-(255,239) encoder.
上傳時(shí)間: 2013-12-09
上傳用戶:CHINA526
資源簡(jiǎn)介:I2C controller Verilog code for altera fpga platform.
上傳時(shí)間: 2016-03-07
上傳用戶:GHF
資源簡(jiǎn)介:Verilog code for 8-bit signed integers....its working
上傳時(shí)間: 2017-03-18
上傳用戶:zhichenglu
資源簡(jiǎn)介:Verilog code for RTC
上傳時(shí)間: 2017-03-27
上傳用戶:zycidjl
資源簡(jiǎn)介:Verilog code for 4 t0 1 multiplexer
上傳時(shí)間: 2013-12-15
上傳用戶:fredguo
資源簡(jiǎn)介:Verilog code for JKflipflop
上傳時(shí)間: 2013-12-31
上傳用戶:asddsd
資源簡(jiǎn)介:Verilog code for alu in RISC processor
上傳時(shí)間: 2017-05-27
上傳用戶:sunjet
資源簡(jiǎn)介:FIR filter basic Verilog code for implementation
上傳時(shí)間: 2013-12-27
上傳用戶:cmc_68289287
資源簡(jiǎn)介:FIR filter basic Verilog code for implementation
上傳時(shí)間: 2013-12-24
上傳用戶:qazxsw
資源簡(jiǎn)介:FIR filter basic Verilog code for implementation
上傳時(shí)間: 2014-11-27
上傳用戶:曹云鵬
資源簡(jiǎn)介:FIR filter basic Verilog code for implementation
上傳時(shí)間: 2013-12-14
上傳用戶:erkuizhang
資源簡(jiǎn)介:FIR filter basic Verilog code for implementation
上傳時(shí)間: 2013-12-24
上傳用戶:tuilp1a
資源簡(jiǎn)介:Verilog code for 3 bit sequence detector
上傳時(shí)間: 2017-06-26
上傳用戶:gdgzhym
資源簡(jiǎn)介:Verilog code for Digital lock
上傳時(shí)間: 2017-07-08
上傳用戶:1159797854
資源簡(jiǎn)介:Verilog code for ADC
上傳時(shí)間: 2013-12-21
上傳用戶:kelimu
資源簡(jiǎn)介:Verilog code for MAC
上傳時(shí)間: 2013-12-29
上傳用戶:李夢(mèng)晗
資源簡(jiǎn)介:Verilog code for dct
上傳時(shí)間: 2014-01-23
上傳用戶:a673761058
資源簡(jiǎn)介:Verilog code for 2D-DCT with detailed documentation.
上傳時(shí)間: 2014-01-14
上傳用戶:zwei41
資源簡(jiǎn)介:i2c code for the Verilog
上傳時(shí)間: 2013-09-04
上傳用戶:DXM35
資源簡(jiǎn)介:完整的jpeg encoder Verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實(shí)現(xiàn)精簡(jiǎn)電路
上傳時(shí)間: 2014-01-20
上傳用戶:waizhang
資源簡(jiǎn)介:something which is useful for rs code design
上傳時(shí)間: 2016-02-14
上傳用戶:zsjinju
資源簡(jiǎn)介:Very good info. for RS-232 transmitter VHDL code .
上傳時(shí)間: 2016-07-14
上傳用戶:極客
資源簡(jiǎn)介:Very good info. for RS-232 receive VHDL code .
上傳時(shí)間: 2016-07-14
上傳用戶:米卡
資源簡(jiǎn)介:Very good info. for RS-232 echo VHDL code .
上傳時(shí)間: 2016-07-14
上傳用戶:zhangyi99104144
資源簡(jiǎn)介:RS[255,223]糾錯(cuò)碼Verilog源碼,包含編碼和解碼模塊,以及testbench等。
上傳時(shí)間: 2014-01-01
上傳用戶:海陸空653
資源簡(jiǎn)介:it is a Verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
上傳時(shí)間: 2017-03-22
上傳用戶:洛木卓
資源簡(jiǎn)介:it is a Verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
上傳時(shí)間: 2014-01-10
上傳用戶:kernaling
資源簡(jiǎn)介:it is a Verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is requir...
上傳時(shí)間: 2014-06-26
上傳用戶:zhuyibin
資源簡(jiǎn)介:it is a Verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
上傳時(shí)間: 2017-03-22
上傳用戶:xymbian
資源簡(jiǎn)介:it is a Verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
上傳時(shí)間: 2013-12-11
上傳用戶:yepeng139