相 關(guān) 資 源

• Verilog code for RS-(255,239) encoder.免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for RS-(255,239) encoder.

  標(biāo)簽： Verilog encoder code 255

  上傳時(shí)間： 2013-12-09

  上傳用戶：CHINA526

• I2C controller Verilog code for altera fpga platform.免費(fèi)下載

  資源簡(jiǎn)介：I2C controller Verilog code for altera fpga platform.

  標(biāo)簽： controller platform Verilog altera

  上傳時(shí)間： 2016-03-07

  上傳用戶：GHF

• Verilog code for 8-bit signed integers....its working免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for 8-bit signed integers....its working

  標(biāo)簽： integers Verilog working signed

  上傳時(shí)間： 2017-03-18

  上傳用戶：zhichenglu

• Verilog code for RTC免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for RTC

  標(biāo)簽： Verilog code RTC for

  上傳時(shí)間： 2017-03-27

  上傳用戶：zycidjl

• Verilog code for 4 t0 1 multiplexer免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for 4 t0 1 multiplexer

  標(biāo)簽： multiplexer Verilog code for

  上傳時(shí)間： 2013-12-15

  上傳用戶：fredguo

• Verilog code for JKflipflop免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for JKflipflop

  標(biāo)簽： JKflipflop Verilog code for

  上傳時(shí)間： 2013-12-31

  上傳用戶：asddsd

• Verilog code for alu in RISC processor免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for alu in RISC processor

  標(biāo)簽： processor Verilog code RISC

  上傳時(shí)間： 2017-05-27

  上傳用戶：sunjet

• FIR filter basic Verilog code for implementation免費(fèi)下載

  資源簡(jiǎn)介：FIR filter basic Verilog code for implementation

  標(biāo)簽： implementation Verilog filter basic

  上傳時(shí)間： 2013-12-27

  上傳用戶：cmc_68289287

• FIR filter basic Verilog code for implementation免費(fèi)下載

  資源簡(jiǎn)介：FIR filter basic Verilog code for implementation

  標(biāo)簽： implementation Verilog filter basic

  上傳時(shí)間： 2013-12-24

  上傳用戶：qazxsw

• FIR filter basic Verilog code for implementation免費(fèi)下載

  資源簡(jiǎn)介：FIR filter basic Verilog code for implementation

  標(biāo)簽： implementation Verilog filter basic

  上傳時(shí)間： 2014-11-27

  上傳用戶：曹云鵬

• FIR filter basic Verilog code for implementation免費(fèi)下載

  資源簡(jiǎn)介：FIR filter basic Verilog code for implementation

  標(biāo)簽： implementation Verilog filter basic

  上傳時(shí)間： 2013-12-14

  上傳用戶：erkuizhang

• FIR filter basic Verilog code for implementation免費(fèi)下載

  資源簡(jiǎn)介：FIR filter basic Verilog code for implementation

  標(biāo)簽： implementation Verilog filter basic

  上傳時(shí)間： 2013-12-24

  上傳用戶：tuilp1a

• Verilog code for 3 bit sequence detector免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for 3 bit sequence detector

  標(biāo)簽： detector sequence Verilog code

  上傳時(shí)間： 2017-06-26

  上傳用戶：gdgzhym

• Verilog code for Digital lock免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for Digital lock

  標(biāo)簽： Verilog Digital code lock

  上傳時(shí)間： 2017-07-08

  上傳用戶：1159797854

• Verilog code for ADC免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for ADC

  標(biāo)簽： Verilog code ADC for

  上傳時(shí)間： 2013-12-21

  上傳用戶：kelimu

• Verilog code for MAC免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for MAC

  標(biāo)簽： Verilog code MAC for

  上傳時(shí)間： 2013-12-29

  上傳用戶：李夢(mèng)晗

• Verilog code for dct免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for dct

  標(biāo)簽： Verilog code for dct

  上傳時(shí)間： 2014-01-23

  上傳用戶：a673761058

• Verilog code for 2D-DCT with detailed documentation.免費(fèi)下載

  資源簡(jiǎn)介：Verilog code for 2D-DCT with detailed documentation.

  標(biāo)簽： documentation detailed Verilog D-DCT

  上傳時(shí)間： 2014-01-14

  上傳用戶：zwei41

• i2c code for the Verilog免費(fèi)下載

  資源簡(jiǎn)介：i2c code for the Verilog

  標(biāo)簽： Verilog code i2c for

  上傳時(shí)間： 2013-09-04

  上傳用戶：DXM35

• 完整的jpeg encoder Verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實(shí)現(xiàn)精簡(jiǎn)電路免費(fèi)下載

  資源簡(jiǎn)介：完整的jpeg encoder Verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實(shí)現(xiàn)精簡(jiǎn)電路

  標(biāo)簽： convolution transection circular encoder

  上傳時(shí)間： 2014-01-20

  上傳用戶：waizhang

• something which is useful for rs code design免費(fèi)下載

  資源簡(jiǎn)介：something which is useful for rs code design

  標(biāo)簽： something design useful which

  上傳時(shí)間： 2016-02-14

  上傳用戶：zsjinju

• Very good info. for RS-232 transmitter VHDL code .免費(fèi)下載

  資源簡(jiǎn)介：Very good info. for RS-232 transmitter VHDL code .

  標(biāo)簽： transmitter Very VHDL good

  上傳時(shí)間： 2016-07-14

  上傳用戶：極客

• Very good info. for RS-232 receive VHDL code .免費(fèi)下載

  資源簡(jiǎn)介：Very good info. for RS-232 receive VHDL code .

  標(biāo)簽： receive Very VHDL good

  上傳時(shí)間： 2016-07-14

  上傳用戶：米卡

• Very good info. for RS-232 echo VHDL code .免費(fèi)下載

  資源簡(jiǎn)介：Very good info. for RS-232 echo VHDL code .

  標(biāo)簽： Very VHDL good echo

  上傳時(shí)間： 2016-07-14

  上傳用戶：zhangyi99104144

• RS[255,223]糾錯(cuò)碼Verilog源碼免費(fèi)下載

  資源簡(jiǎn)介：RS[255,223]糾錯(cuò)碼Verilog源碼，包含編碼和解碼模塊，以及testbench等。

  標(biāo)簽： Verilog 255 223 RS

  上傳時(shí)間： 2014-01-01

  上傳用戶：海陸空653

• it is a Verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x免費(fèi)下載

  資源簡(jiǎn)介：it is a Verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.

  標(biāo)簽： synthesize simulator modelsim interin

  上傳時(shí)間： 2017-03-22

  上傳用戶：洛木卓

• it is a Verilog code written for digital watch in modelsim simulator and it will synthesize in xin免費(fèi)下載

  資源簡(jiǎn)介：it is a Verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]

  標(biāo)簽： synthesize simulator modelsim digital

  上傳時(shí)間： 2014-01-10

  上傳用戶：kernaling

• it is a Verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8免費(fèi)下載

  資源簡(jiǎn)介：it is a Verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is requir...

  標(biāo)簽： synthesize simulator modelsim Verilog

  上傳時(shí)間： 2014-06-26

  上傳用戶：zhuyibin

• it is a Verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have免費(fèi)下載

  資源簡(jiǎn)介：it is a Verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.

  標(biāo)簽： controller synthesize Verilog traffic

  上傳時(shí)間： 2017-03-22

  上傳用戶：xymbian

• it is a Verilog code written for MELAY state machine based UART and it wll synthesize in xinlix免費(fèi)下載

  資源簡(jiǎn)介：it is a Verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]

  標(biāo)簽： synthesize Verilog machine written

  上傳時(shí)間： 2013-12-11

  上傳用戶：yepeng139