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• UART Transmitter. VHDL code and its testbench.免費(fèi)下載

  資源簡(jiǎn)介：UART Transmitter. VHDL code and its testbench.

  標(biāo)簽： Transmitter testbench UART VHDL

  上傳時(shí)間： 2017-08-30

  上傳用戶：cmc_68289287

• Shift Register. VHDL code and its testbench.免費(fèi)下載

  資源簡(jiǎn)介：Shift Register. VHDL code and its testbench.

  標(biāo)簽： testbench Register Shift VHDL

  上傳時(shí)間： 2013-12-18

  上傳用戶：wlcaption

• Very good info. for RS-232 Transmitter VHDL code .免費(fèi)下載

  資源簡(jiǎn)介：Very good info. for RS-232 Transmitter VHDL code .

  標(biāo)簽： Transmitter Very VHDL good

  上傳時(shí)間： 2016-07-14

  上傳用戶：極客

• The document explains the Alamouti s idea in creating an stbc code and its specifications免費(fèi)下載

  資源簡(jiǎn)介：The document explains the Alamouti s idea in creating an stbc code and its specifications

  標(biāo)簽： specifications Alamouti document creating

  上傳時(shí)間： 2013-12-19

  上傳用戶：cx111111

• RS232 Transmitter VHDL Code免費(fèi)下載

  資源簡(jiǎn)介：RS232 Transmitter VHDL Code

  標(biāo)簽： Transmitter Code VHDL 232

  上傳時(shí)間： 2013-12-17

  上傳用戶：小寶愛考拉

• xinlinx s VHDL code model and user guider免費(fèi)下載

  資源簡(jiǎn)介：xinlinx s VHDL code model and user guider

  標(biāo)簽： xinlinx guider model VHDL

  上傳時(shí)間： 2015-10-19

  上傳用戶：l254587896

• DAC converter design with Verilog code and testbench免費(fèi)下載

  資源簡(jiǎn)介：DAC converter design with Verilog code and testbench

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  上傳時(shí)間： 2014-01-23

  上傳用戶：yyyyyyyyyy

• The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device for data免費(fèi)下載

  資源簡(jiǎn)介：The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device for data communication in the field of telecommunication. There are different versions of UARTs in the industry.

  標(biāo)簽： Asynchronous Transmitter widely-used Universal

  上傳時(shí)間： 2014-11-06

  上傳用戶：star_in_rain

• UART VHDL code : include tx,rx,parity bit control免費(fèi)下載

  資源簡(jiǎn)介：UART VHDL code : include tx,rx,parity bit control

  標(biāo)簽： include control parity UART

  上傳時(shí)間： 2017-05-10

  上傳用戶：開懷常笑

• this is the VHDL code of arithmetic and logic unit of 16 bit microprocessor.免費(fèi)下載

  資源簡(jiǎn)介：this is the VHDL code of arithmetic and logic unit of 16 bit microprocessor.

  標(biāo)簽： microprocessor arithmetic logic this

  上傳時(shí)間： 2013-12-07

  上傳用戶：jcljkh

• This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.免費(fèi)下載

  資源簡(jiǎn)介：This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.

  標(biāo)簽： Transmitter interface Sparton Tested

  上傳時(shí)間： 2014-01-25

  上傳用戶：zxc23456789

• UART Transmitter and receiver mocros免費(fèi)下載

  資源簡(jiǎn)介：UART Transmitter and receiver mocros

  標(biāo)簽： Transmitter receiver mocros UART

  上傳時(shí)間： 2013-12-25

  上傳用戶：bakdesec

• LFSR is linear fedback shift reg is fine dirnf shifting process.VHDL code to understand its function免費(fèi)下載

  資源簡(jiǎn)介：LFSR is linear fedback shift reg is fine dirnf shifting process.VHDL code to understand its functioning

  標(biāo)簽： understand function shifting fedback

  上傳時(shí)間： 2017-09-05

  上傳用戶：sevenbestfei

• CAM is useful VHDL code to understand its architecture which helps to write any code免費(fèi)下載

  資源簡(jiǎn)介：CAM is useful VHDL code to understand its architecture which helps to write any code

  標(biāo)簽： code architecture understand useful

  上傳時(shí)間： 2017-09-05

  上傳用戶：天涯

• VHDL 關(guān)于2DFFT設(shè)計(jì)程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL VHDL code. The details can be 免費(fèi)下載

  資源簡(jiǎn)介：VHDL 關(guān)于2DFFT設(shè)計(jì)程序 u scinode1 &#8764 scinode9.vhd: Every SCI node RTL VHDL code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support ...

  標(biāo)簽： scinode1 scinode details 2DFFT

  上傳時(shí)間： 2014-12-02

  上傳用戶：15071087253

• This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multip免費(fèi)下載

  資源簡(jiǎn)介：This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.

  標(biāo)簽： adder 8bit multiplier consist

  上傳時(shí)間： 2014-08-21

  上傳用戶：zhangliming420

• CPLD VHDL CODE非常好的參考資料免費(fèi)下載

  資源簡(jiǎn)介：CPLD VHDL CODE非常好的參考資料

  標(biāo)簽： CPLD CODE VHDL 參考資料

  上傳時(shí)間： 2013-08-14

  上傳用戶：songkun

• Digital DATCOM Source Code and Examples免費(fèi)下載

  資源簡(jiǎn)介：Digital DATCOM Source Code and Examples

  標(biāo)簽： Examples Digital DATCOM Source

  上傳時(shí)間： 2015-01-10

  上傳用戶：Divine

• HT1380 source code, ht1380.c is source code and ht1380.h is head file免費(fèi)下載

  資源簡(jiǎn)介：HT1380 source code, ht1380.c is source code and ht1380.h is head file

  標(biāo)簽： 1380 source code ht

  上傳時(shí)間： 2015-04-08

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• uCOS-II 2.80 original source code and documentation... zip password : ucos免費(fèi)下載

  資源簡(jiǎn)介：uCOS-II 2.80 original source code and documentation... zip password : ucos

  標(biāo)簽： documentation original password uCOS-II

  上傳時(shí)間： 2015-04-13

  上傳用戶：彭玖華

• Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select免費(fèi)下載

  資源簡(jiǎn)介：Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY,...

  標(biāo)簽： instruction additional language example

  上傳時(shí)間： 2014-01-17

  上傳用戶：yyyyyyyyyy

• This a simple compressor based on aplib, yoda s Kernel code, and my own stuffing around. It only ha免費(fèi)下載

  資源簡(jiǎn)介：This a simple compressor based on aplib, yoda s Kernel code, and my own stuffing around. It only has one function with MANY limitations at the moment, but it is desinged for demo purposes only so it don t matter.

  標(biāo)簽： compressor stuffing Kernel simple

  上傳時(shí)間： 2013-12-24

  上傳用戶：13215175592

• VS10xx Standalone Player program code and pdf document免費(fèi)下載

  資源簡(jiǎn)介：VS10xx Standalone Player program code and pdf document

  標(biāo)簽： Standalone document program Player

  上傳時(shí)間： 2014-01-08

  上傳用戶：lnnn30

• the file contain many matlab signal source code and many example .免費(fèi)下載

  資源簡(jiǎn)介：the file contain many matlab signal source code and many example .

  標(biāo)簽： many contain example matlab

  上傳時(shí)間： 2014-01-20

  上傳用戶：com1com2

• Back propagation neural networks and its Application: Time-Series Forecasting Prediction of the Annu免費(fèi)下載

  資源簡(jiǎn)介：Back propagation neural networks and its Application: Time-Series Forecasting Prediction of the Annual Number of Sunspots

  標(biāo)簽： Application propagation Time-Series Forecasting

  上傳時(shí)間： 2015-05-13

  上傳用戶：離殤

• OFDM信號(hào)及其頻譜 OFDM signal and its spectrum ( Guard Interval insertion )免費(fèi)下載

  資源簡(jiǎn)介：OFDM信號(hào)及其頻譜 OFDM signal and its spectrum ( Guard Interval insertion )

  標(biāo)簽： OFDM insertion Interval spectrum

  上傳時(shí)間： 2015-05-17

  上傳用戶：wang5829

• Analyse the uboot code and let you know how to adopt it免費(fèi)下載

  資源簡(jiǎn)介：Analyse the uboot code and let you know how to adopt it

  標(biāo)簽： Analyse adopt uboot code

  上傳時(shí)間： 2014-10-12

  上傳用戶：電子世界

• UART的VHDL實(shí)現(xiàn)代碼 分模塊設(shè)計(jì)和狀態(tài)機(jī)設(shè)計(jì) 不錯(cuò)的免費(fèi)下載

  資源簡(jiǎn)介：UART的VHDL實(shí)現(xiàn)代碼 分模塊設(shè)計(jì)和狀態(tài)機(jī)設(shè)計(jì) 不錯(cuò)的，用它沒錯(cuò)

  標(biāo)簽： UART VHDL 代碼 分

  上傳時(shí)間： 2014-01-26

  上傳用戶：zhangliming420

• UART 的VHDL源代碼。可在ISE, Max-Plus II,等開發(fā)環(huán)境下實(shí)現(xiàn)。免費(fèi)下載

  資源簡(jiǎn)介：UART 的VHDL源代碼。可在ISE, Max-Plus II,等開發(fā)環(huán)境下實(shí)現(xiàn)。

  標(biāo)簽： Max-Plus UART VHDL ISE

  上傳時(shí)間： 2013-12-16

  上傳用戶：天涯

• FPGA/CPLD應(yīng)用,UART通訊VHDL原碼.免費(fèi)下載

  資源簡(jiǎn)介：FPGA/CPLD應(yīng)用,UART通訊VHDL原碼.

  標(biāo)簽： FPGA CPLD UART VHDL

  上傳時(shí)間： 2015-06-23

  上傳用戶：ve3344