library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_STD.all;-- synopsys translate_offlibrary UNISIM;use UNISIM.vcomponents.all;-- synopsys translate_onentity sdrm is--generic (DATA_MSB : integer := 31;--	 ADDR_MSB : integer := 31);port (	sd_data : inout std_logic_vector(31 downto 0);	AD : inout std_logic_vector(31 downto 0);	sd_add : out std_logic_vector(10 downto 0);	sd_ras : out std_logic;	sd_cas : out std_logic;	sd_we : out std_logic;	sd_ba : out std_logic;	Clk_SDp : out std_logic;	sd_cke : out std_logic;	sd_cs1 : out std_logic;	sd_cs2 : out std_logic;	sd_dqm : out std_logic_vector(3 downto 0);	Reset : in std_logic;	Clkp : in std_logic;	Clk_FBp : in std_logic;	we_rn : in std_logic;	data_addr_n : in std_logic);end entity sdrm;architecture sdrm_arch of sdrm is constant DATA_MSB : integer := 31;constant ADDR_MSB : integer := 31;signal logic1 : std_logic := '1';signal logic0 : std_logic := '0';signal sd_add_op : unsigned(10 downto 0);signal sd_data_i : std_logic_vector(DATA_MSB downto 0);signal AD_i : unsigned(DATA_MSB downto 0);signal sd_data_reg : std_logic_vector(DATA_MSB downto 0);signal sd_cke_o : std_logic := '1';signal sd_cs1_o : std_logic := '0';signal sd_cs2_o : std_logic := '0';signal sd_ba_op : std_logic;signal ready_o : std_logic;signal sd_dqm_o : std_logic_vector(3 downto 0) := "0000";signal Reset_i : std_logic;signal sd_data_o : std_logic_vector(31 downto 0);signal sd_data_t : std_logic_vector(DATA_MSB downto 0);signal sd_data_R : std_logic_vector(DATA_MSB downto 0);signal AD_o : std_logic_vector(DATA_MSB downto 0);signal sd_add_o : unsigned(10 downto 0);signal sd_ba_o : std_logic;signal sd_cas_o : std_logic;signal sd_ras_o : std_logic;signal sd_we_o : std_logic;signal sd_doe_n : std_logic_vector(3 downto 0);signal sd_doe_np : std_logic_vector(3 downto 0);signal Clk_i : std_logic;signal Clk_j : std_logic;signal Clk0A : std_logic;signal Clk0B : std_logic;signal Clk0C : std_logic;signal Locked2 : std_logic;signal Locked1 : std_logic;signal Locked_i : std_logic;signal Locked_j : std_logic;signal Clk_FB : std_logic;signal Clk : std_logic;signal sd_ras_op : std_logic;signal sd_cas_op : std_logic;signal sd_we_op : std_logic;signal write_st : std_logic;signal AD_tri : std_logic;signal Add_reg : unsigned(ADDR_MSB downto 0);signal AD_reg : unsigned(ADDR_MSB downto 0);signal rcd_c_max : unsigned(1 downto 0);signal cas_lat_max : unsigned(1 downto 0);signal burst_max : unsigned(2 downto 0);signal Act_st : std_logic_vector(2 downto 0);signal ki_max : unsigned(3 downto 0);signal ref_max : unsigned(15 downto 0);signal data_addr_n_reg : std_logic;signal we_rn_reg : std_logic;signal data_addr_n_i : std_logic;signal we_rn_i : std_logic;signal kid : std_logic;signal auto_ref_out : std_logic;signal auto_ref_in : std_logic; -- := auto_ref_out;signal unused1, unused2, unused3 : std_logic;signal rcd_end : std_logic;signal Clk_SDp_int : std_logic;component sys_int generic (	ADDR_MSB : integer := 31;	DATA_MSB : integer := 31;	CYCLE : integer := 8;	HALF_CYCLE : integer := 4 );port (	Add_reg : out unsigned(ADDR_MSB downto 0);	sd_data_reg : out std_logic_vector(DATA_MSB downto 0);	Act_st : out std_logic_vector(2 downto 0);	write_st : out std_logic;	rcd_c_max : out unsigned(1 downto 0);	cas_lat_max : out unsigned(1 downto 0);	burst_max : out unsigned(2 downto 0);	ki_max : out unsigned(3 downto 0);	ref_max : out unsigned(15 downto 0);	AD_reg : in unsigned(DATA_MSB downto 0);	Locked : in std_logic;	Clk_i : in std_logic;	data_addr_n_i : in std_logic;	we_rn_i : in std_logic;	data_addr_n_reg : in std_logic;	we_rn_reg : in std_logic);end component;component sdrm_t port (	sd_add_o: out unsigned(10 downto 0);	sd_ras_o: out std_logic;	sd_cas_o: out std_logic;	sd_we_o: out std_logic;	sd_ba_o: out std_logic;	ready_o: out std_logic;	Locked_j: out std_logic;	Locked_i: out std_logic;	kid: out std_logic;	auto_ref_out: out std_logic;	rcd_end: out std_logic;	sd_doe_n: out std_logic_vector(3 downto 0);	AD_tri: out std_logic;	write_st: in std_logic;	auto_ref_in: in std_logic;	Locked1: in std_logic;	Locked2: in std_logic;	Clk_i: in std_logic;	Clk_j: in std_logic;	Act_st: in std_logic_vector(2 downto 0);	rcd_c_max: in unsigned(1 downto 0);	cas_lat_max: in unsigned(1 downto 0);	burst_max: in unsigned(2 downto 0);	ki_max: in unsigned(3 downto 0);	ref_max: in unsigned(15 downto 0);	Add_reg: in unsigned(21 downto 2));end component;component IBUFG port (   O : out std_logic;   I : in std_logic );end component;component CLKDLL port (   CLK0 : out std_logic;   CLK90 : out std_logic;   CLK180 : out std_logic;   CLK270 : out std_logic;   CLK2X : out std_logic;   CLKDV : out std_logic;   LOCKED : out std_logic;   CLKIN : in std_logic;   CLKFB : in std_logic;   RST : in std_logic );end component;component IBUF port (   O : out std_logic;   I : in std_logic );end component;component BUFG port (   O : out std_logic;   I : in std_logic );end component;component OBUF_F_16 port (   O : out std_logic;   I : in std_logic );end component;component IOBUF_F_12 port (   O : out std_logic;   IO : inout std_logic;   I : in std_logic;   T : in std_logic );end component;component OBUF_F_12 port (   O : out std_logic;   I : in std_logic );end component;